Floating-point adder performing floating-point and integer operations

A floating-point adder unit performing an arithmetic operation on a first integer operand and a second integer operand, each one of the integer operands having a plurality of most significant bits and a plurality of least significant bits, the floating-point adder unit comprising:

• exponent logic to add the most significant bits of the first integer operand with the most significant bits of the second integer operand and to generate a first output representing the most significant bits of a result of the aritlunetic operation;
• co-efficient logic to add the least significant bits of the first integer operand with the least significant bits of the second integer operand and to generate a second output representing the least significant bits of the result of the arithmetic operation;
• and
• carry logic to add a carry-out bit from the second output to the first output;
• wherein the first output and the second output represent a result for the arithmetic operation.

A system comprising:

• a memory to store floating-point instructions for execution by a processor;
• a bus;
• and
• a processor operatively coupled to the memory by the bus, the processor including a floating-point adder unit to perform addition, subtraction, and compare arithmetic operations on both integer operands and floating-point operands loaded from the memory over the bus, wherein the floating-point adder includes:
• exponent logic to add most significant bits of a first integer operand with most significant bits of a second integer operand and to generate a first output representing most significant bits of a result of an integer operation;
• co-efficient logic to add least significant bits of the first integer operand with least significant bits of the second integer operand and to generate a second output representing the least significant bits of the result of the integer operation;
• and
• carry logic to add a carry bit from the second output to the first output and to generate a result for the arithmetic operation.

An article comprising:

• a floating-point adder unit to perform addition, subtraction, and compare arithmetic operations on both interger operands and floting-point operands, wherein the floating-point adder unit further comprises;
• exponent logic to add most significant bits of a firs interger operand with most significant bits of a second integer operand and to generate a first output representing most significant bits of a result of an interger operation;
• co-efficient logic to add least significant bits of the first interger operand with least significant bits of the second interger operand and to generate a second output representing the least significant bits of the result of the integer operation;
• and
• carry logic to add a carry bit from the second output to the first output and to generate a result for the arithmetic operation.