Amplifier with suppression of harmonics

A differential linear amplifier having an input and an output, comprising:

• a main differential amplification circuit, comprising:
• a first differential pair of transistors arranged to amplify a differential input signal that is input to the amplifier so as to generate a differential output signal at the output of the amplifier, the transistors comprising respective bases that are coupled to receive the input signal and respective collectors and respective emitters;
• at least one first resistor, having an effective resistance R1, connected between the emitters;
• and
• a second differential pair of transistors coupled together in a common-base structure and including emitters coupled respectively to the collectors of the transistors in the first differential pair and collectors coupled to the output of the amplifier;
• and
• an odd-order compensation circuit, comprising:
• a third differential pair of transistors comprising respective bases that are coupled respectively to the collectors of the first differential pair of transistors and respective collectors that are coupled to the output of the amplifier so as to generate a harmonic compensation signal at the output of the amplifier, and further comprising respective emitters;
• and
• at least one second resistor, having an effective resistance R2, connected between the emitters of the third differential pair of transistors,
• wherein the resistances R1 and R2 are given substantially by:
• r 1 ⁡ ( r 2 , m ) = 2 · m · ( 1 + 0.5 · r 2 ) 4 + ( 1 - m ) ( 1 - m ) · [ ( 1 + 0.5 · r 2 ) 3 - 1 ] ,
• wherein r i = R i · I i · q k · T ,
• for an index i = 1 , 2 , I 1 I 2 = m 1 - m
• m a parameter such that 0<m<1, I1 is a DC bias current of the transistors in the first differential pair, I2 is a DC bias current of the transistors in the second differential pair, q is a unit of elementary charge, k is Boltzmann's constant, and T is an operating temperature of the transistors.

A method for linearizing an amplifier, comprising:

• coupling a main differential amplification circuit to receive a differential input signal at an input of the amplifier and to generate a differential output signal at an output of the amplifier;
• sampling an odd-order harmonic current in the main differential amplification circuit;
• amplifying the sampled odd-order harmonic current in an odd-order compensation circuit so as to generate an odd-order compensation signal;
• sampling an even-order harmonic current in the main differential amplification circuit;
• amplifying the sampled even-order harmonic current in an even-order compensation circuit so as to generate an even-order compensation signal;
• and
• subtracting the odd-order and even-order compensation signals from the differential output signal.

A method for linearizing a differential amplifier having an input and an output, comprising:

• providing a main differential amplification circuit, comprising:
• a first differential pair of transistors arranged to amplify a differential input signal that is input to the amplifier so as to generate a differential output signal at the output of the amplifier, the transistors comprising respective bases that are coupled to receive the input signal and respective collectors and emitters;
• at least one first resistor, having an effective resistance R1, connected between the emitters;
• and
• a second differential pair of transistors coupled together in a common-base structure and including emitters coupled respectively to the collectors of the transistors in the first differential pair and collectors coupled to the output of the amplifier;
• and
• providing an odd-order compensation circuit, comprising:
• a third differential pair of transistors comprising respective bases that are coupled respectively to the collectors of the first differential pair of transistors and respective collectors that are coupled to the output of the amplifier so as to generate a harmonic compensation signal at the output of the amplifier, and further comprising respective emitters;
• and
• at least one second resistor, having an effective resistance R2, connected between the emitters of the third differential pair of transistors;
• and
• setting the resistances R1 and R2 so that the resistances are given substantially by:
• r 1 ⁡ ( r 2 , m ) = 2 · m · ( 1 + 0.5 · r 2 ) 4 + ( 1 - m ) ( 1 - m ) · [ ( 1 + 0.5 · r 2 ) 3 - 1 ] ,
• wherein r i = R i · I i · q k · T ,
• for an index i = 1 , 2 , I 1 I 2 = m 1 - m
• m a parameter such that 0<m<1, I1 is a DC bias current of the transistors in the first differential pair, I2 is a DC bias current of the transistors in the third differential pair, q is a unit of elementary charge, k is Boltzmann's constant, and T is an operating temperature of the transistors.