Method for creating circuit redundancy in programmable logic devices
AssigneeInterface & Control Systems, Inc.
InventorsWalter P. Schiefele, Robert O. Krueger
Life of this patent
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Abstract
In a field programmable gate array (FPGA) allowing dynamic reconfiguration in time multiplexing fashion, duplicate copies are configured in a time multiplexing manner which are functionally identical to a primary circuit specified for a predetermined FPGA's application. The primary and duplicate circuits are interrogated by a voting circuit which determines the existence of a faulted circuit in order to eliminate the faulted circuit from the operation of the FPGA. In this manner, without physical addition of redundant circuits, fault tolerancy for the FPGA is provided to minimize the cost, weight, volume, heat and energy associated issues of conventional redundance techniques.
Claims47
A method for creating circuit redundancy in programmable logic devices, comprising the steps of:
- (a) establishing a programmable logic device containing a plurality of structural elements,
- (b) configuring a first portion of said plurality of structural elements at a first time slice into a primary circuit for a predetermined application,
- (c) identifying at least a second portion of said plurality of structural elements having the least overlap with the structural elements of said first portion thereof,
- (d) configuring said structural elements at a second time slice of said at least second portion thereof into a duplicate circuit substantially functionally identical with respect to said primary circuit, and
- (e) comparing performance of said primary circuit and said duplicate circuit in a time-multiplexing fashion.
A method for creating fault tolerance in programmable logic devices, comprising the steps of:
- configuring at a first time slice, a primary group of a plurality of structural elements of a programmable logic device into a primary circuit for a predetermined application;
- defining a plurality of sequential time slices following said first time slice;
- identifying in each of said time slices a respective Nth duplicate group of said plurality of the structural elements;
- configuring said respective duplicate group of the structural elements into a duplicate circuit substantially functionally identical to said primary circuit;
- comparing performance of said primary circuit and said duplicate circuit in time-multiplexing fashion;
- and
- excluding at least one of said primary circuit and said duplicate circuit from operation subsequent to disagreement in performance being detected in said comparing step.
A programmable logic device with fault tolerance, comprising:
- a plurality of configurable structural elements;
- means for defining a plurality of time slices,
- configuration means containing configuration data and coupled to said configurable structural elements for:
- (a) configuring a primary group thereof into a primary circuit in a 1st time slice of said plurality of time slices, and
- (b) configuring an Nth duplicate group of the configurable structural elements into a duplicate circuit substantially functionally identical to said primary circuit in a (N+1)th time slice of said plurality of time slices, wherein N≧1;
- means for identifying said Nth duplicate group of the configurable structural elements having the least overlap with the configurable structural elements occupied in said primary circuit and in any of (N−1) duplicate circuits;
- and
- voting means for interrogating said primary circuit and said duplicate circuits in time-multiplexing fashion for comparing performance thereof.
A method for creating circuit redundancy in field programmable gate array (FPGA), comprising the steps of:
- in a FPGA containing a plurality of configurable structural elements,
- a) defining a plurality of time slices, and
- b) configuring, in a time-multiplexing fashion, a plurality of functionally substantially identical circuits from the structural elements of said FPGA having the least overlap with the structural elements occupied in any previous of said plurality of time slices.
Dependencies are inferred from the claim text.