Architecture and method for partially reconfiguring an FPGA
AssigneeXilinx, Inc.
InventorsSteven P. Young, Trevor J. Bauer
Life of this patent
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Abstract
An FPGA architecture and method enables partial reconfiguration of selected configurable logic blocks (CLBs) connected to an address line without affecting other CLBs connected to the same address line. Partial reconfiguration at a memory cell resolution is achieved by manipulating the input voltages applied to the address and data lines of an FPGA so that certain memory cells are programmed while other memory cells are not programmed. In addition, partial reconfiguration at a CLB resolution can be achieved by hardwiring the FPGA to enable selection of individual CLBs for reconfiguration.
Claims25
A method for partially configuring a field programmable gate array (FPGA), the FPGA having an array of configurable logic blocks (CLBS) connected by multiple address lines and multiple data line pairs, the method comprising:
- reconfiguring one or more first CLBs addressed by at least one address line;
- and
- simultaneously preventing reconfiguration of second CLBs addressed by the address line.
A method for partially configuring a field programmable gate array (FPGA), the FPGA having multiple address lines, multiple complementary data line pairs, and a plurality of mask lines, each of which serves at least one of the data line pairs, the method comprising:
- applying a voltage to an address line common to an array of memory cells;
- using the mask lines to select first complementary data lines pairs connected to the memory cells being reconfigured and deselect second complementary data line pairs connected to the memory cells not being reconfigured;
- and
- selectively reconfiguring one or more memory cells within the array by applying first data values to the first complementary data line pairs and applying second data values to the second complementary data line pairs.
A field programmable gate array (FPGA), comprising:
- multiple memory cells;
- multiple address lines and multiple complementary data line pairs to access the memory cells;
- multiple mask lines for corresponding data line pairs;
- a mask register to select certain of the mask lines;
- and
- structure for selectively reconfiguring at least one of the memory cells by applying a voltage to an address line common to an array of memory cells and using the mask lines to select first complementary data line pairs connected to the memory cells being reconfigured and deselect second complementary data line pairs connected to the memory cells not being reconfigured, the selected first data line pairs receiving first data values and the deselected second data line pairs receiving second data values.
A field programmable gate array (FPGA), comprising:
- an array of configurable logic blocks (CLBs), each CLB having a local address line and multiple data lines;
- multiple non-local address lines;
- multiple addressable mask lines;
- a register to receive programming data for programming the CLBs, the data stored in the register being carried on the data lines to the CLBs;
- and
- logic to connect the mask lines and the non-local address lines to corresponding local address lines at individual CLBs so that selection of a mask line and selection of a non-local address line enables selection of the corresponding local address line to selectively program an individual CLB.
A system for programming a field programmable gate array (FPGA), the FPGA having an array of configurable logic blocks (CLBs) connected by multiple address lines and multiple data line pairs, the system comprising:
- means for reconfiguring one or more first CLBs addressed by at least one address line;
- and
- means for simultaneously preventing reconfiguration of second CLBs addressed by the address line.
A system for programming a field programmable gate array (FPGA), the FPGA having an array of memory cells connected by multiple address lines and multiple data line pairs, and at least one mask line for each of the data line pairs, the system comprising:
- an address select unit to apply a voltage to an address line common to an array of memory cells and control the mask lines to select first complementary data lines pairs connected to the memory cells being reconfigured and deselect second complementary data line pairs connected to the memory cells not being reconfigured.
A system for programming a field programmable gate array (FPGA), the FPGA having an array of memory cells connected by multiple address lines and multiple data line pairs, the system comprising:
- a data select unit to apply first data values to first complementary data line pairs connected to first memory cells from the array that are being programmed and to apply second data values to second complementary data line pairs connected to second memory cells from the array that are not being programmed, wherein the data select unit is configured to apply a combination of a binary 1 and a binary 0 to the first complementary data line pairs and a binary 1 to each of the second complementary data line pairs.
A field programmable gate array (FPGA), comprising:
- an array of configurable logic blocks (CLBs), each CLB having at least one local address line and multiple data lines;
- and
- an addressable data register to receive programming data for programming the CLBs via the data lines.
Dependencies are inferred from the claim text.