Bus architecture employing varying width uni-directional command bus

A method for communicating between devices attached to a communication bus in a computer system, said communication bus including a command bus portion, said method comprising the steps of:

• requesting control of said command bus portion by a first device attached to said communication bus during a first bus cycle;
• receiving a grant of control of said command portion by said first device during a second bus cycle;
• transmitting command information for a bus command on a first link of said command bus portion from said first device to a repeater unit during a plurality of consecutive bus cycles beginning with a third bus cycle and ending on a fourth bus cycle, said third and fourth bus cycles occurring a respective pre-defined number of cycles after said second bus cycle;
• and
• re-transmitting said command information on a second link of said command bus portion from a repeater unit to second device attached to said communication bus during a fifth bus cycle, said fifth bus cycle occurring a pre-defined number of cycles after said second bus cycle, wherein command information transmitted on said first link during multiple cycles is transmitted on said second link in a single cycle.

A processor for use in a multi-processor computer system, said computer system having a communications bus for communicating among processors and memory, said communications bus having a command bus portion for transmitting commands from an originating processor to other devices attached to the communications bus, said processor comprising:

• a command bus request port for requesting the right to transmit a command on said command bus portion from an arbitrator;
• a command bus grant port for receiving bus grant from said arbitrator;
• a command output port having a plurality N of output pins for transmitting bus commands;
• a command receive port having a plurality M of input pins for receiving bus commands, wherein M>N, the number of input pins M being sufficient to receive a bus command in one bus cycle;
• and
• interface logic for transmitting bus commands on said command output port responsive to receiving bus grant from said arbitrator, wherein a bus command is transmitted from said plurality of output pins during a plurality of consecutive bus cycles beginning with a first cycle occurring a first pre-defined number of bus cycles after said processor receives bus grant and ending with a second bus cycle occurring a second pre-defined number of bus cycles after said processor receives bus grant.