Programmable impedance control circuit

A programmable impedance control circuit, comprising:

• a voltage divider, comprising:
• MOS array supplied with a first voltage;
• and
• an external resistance having an external impedance, said external resistance equal to N times said external impedance;
• said voltage divider outputting a second voltage;
• and
• a reference voltage generator adapted to generate a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for the second voltage, wherein M times internal impedance is used for N times external impedance, wherein N and M are integer numbers and M does not equal N.

A programmable impedance control circuit for controlling a circuit having M times internal impedance and N times external impedance (N≠M) wherein M and N are integer numbers, comprising:

• a first circuit including a first MOS array being supplied with a first voltage, an external resistance having N times external impedance, a pad outputting a second voltage obtained in combination of the first MOS array and the external resistance, a first reference voltage generator for generating a first reference voltage corresponding to N/(N+M) times of the first voltage as a first reference voltage for the second voltage outputted from the pad, a first comparator for comparing the second voltage with the first reference voltage to output an impedance in compliance the first reference voltage for the second voltage, and a first counter for generating a first signal corresponding to the impedance outputted from the first comparator to output the first signal to an up-driver and up-terminator and at the same time feeding back the first signal to the first MOS array;
• and
• a second circuit including a second MOS array being supplied with the first voltage and receiving the first signal outputted from the first counter, a third MOS array connected to the second MOS array at one terminal and connected to ground at another terminal, a second comparator for comparing a third voltage obtained by combination of the second MOS array and the third MOS array with a second reference voltage, the second reference voltage being not equal to the first reference voltage, to output an impedance in compliance the second reference voltage for the third voltage, and a second counter for generating a second signal corresponding to the impedance outputted from the second comparator to output the second signal to a down-driver and down-terminator and at the same time feeding back the second signal to the third MOS array.