MIS semiconductor device with low on resistance and high breakdown voltage

A semiconductor device having a MIS structure, the semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate;
• a base region of the first conductivity type formed selectively in the surface portion of the offset region;
• a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region, the drain region being spaced apart from the base region;
• a source region of the second conductivity type formed selectively in the surface portion of the base region;
• a gate insulation film at least on the extended portion of the base region extended between the source region and the offset region;
• a gate electrode on the gate insulation film;
• a source electrode on the source region;
• a drain electrode on the drain region;
• a field insulation film formed selectively on the offset region;
• and
• a spiral thin film on the field insulation film, an end of the spiral thin film being connected to the drain electrode, another end of the spiral thin film being connected to the source electrode, the spiral thin film being formed of multiple pn-diodes connected in series, the spiral thin film surrounding the drain electrode, the spiral thin film comprising a thin film resistor branching from the midpoint of the series connection of the pn-diodes, the thin film resistor being formed along the drain electrode and the source electrode.

A semiconductor device having a MIS structure, the semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a base region of the first conductivity type formed selectively in the surface portion of the semiconductor substrate;
• a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate;
• a heavily doped source region of the second conductivity type formed selectively in the surface portion of the base region;
• a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region;
• a gate insulation film at least on the extended portion of the base region extended between the source region and the offset region;
• a gate electrode on the gate insulation film;
• a source electrode on the source region;
• a drain electrode on the drain region;
• a field insulation film formed selectively on the offset region;
• a first thin film comprising pn-diodes connected in series;
• a first thin resistive layer;
• and
• a second thin film comprising pn-diodes connected in series;
• the source electrode surrounding the drain electrode or the drain electrode surrounding the source electrode;
• an end of the first thin film being connected to the source electrode;
• another end of the first thin film being connected to an end of the first thin resistive layer;
• another end of the first thin resistive layer being connected to an end of the second thin film;
• and
• another end of the second thin film being connected to the drain electrode.

A semiconductor device having a MIS structure, the semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a base region of the first conductivity type formed selectively in the surface portion of the semiconductor substrate;
• a lightly doped offset region of a second conductivity type formed selectively in the surface portion of the semiconductor substrate;
• a heavily doped source region of the second conductivity type formed selectively in the surface portion of the base region;
• a heavily doped drain region of the second conductivity type formed selectively in the surface portion of the offset region;
• a gate insulation film at least on the extended portion of the base region extended between the source region and the offset region;
• a gate electrode on the gate insulation film;
• a source electrode on the source region;
• a drain electrode on the drain region;
• a field insulation film formed selectively on the offset region;
• a first thin film comprising pn-diodes connected in series;
• a thin resistive layer;
• and
• a second thin film comprising pn-diodes connected in series;
• the source electrode surrounding the drain electrode or the drain electrode surrounding the source electrode;
• the thin resistive layer being between the source electrode and drain electrode, and the thin resistive layer turning around along the source electrode and the drain electrode;
• an end of the first thin film being connected to the source electrode;
• another end of the first thin film being connected to a first location of the thin resistive layer;
• an end of the second thin film being connected to a second location of the thin resistive layer;
• and
• another end of the second thin film being connected to the drain electrode.