Estimation of timing offsets in parallel A/D converters

Abstract

A parallel analog-to-digital converter device has parallel converter cells signal (u) appearing at an input line. The cells are clocked by a common clock signal delayed by delay elements for the respective cell. Timing errors of the sampling times are determined in a calculation unit receiving the output signals of the cells. The output signal of the total converter is compensated by a compensation device for the determined timing errors to provide corrected sampled values on the output line of the converter. In the calculation unit sums of squared differences of the sampled values for successive cells are calculated which by simple operations provide estimates of the timing errors. In the calculation unit also a variance of noise superposed on the sampled values can be estimated and then used to correct the calculated sums for the variance. The input signal is basically unknown and the determination of the timing errors works without using any calibration signal. However, the energy spectrum of the signal should be concentrated to lower frequencies. By compensating for the timing errors the accuracy of the A/D converter is significantly improved.

Dependencies are inferred from the claim text.