Reduced power testing with equally divided scan paths

An integrated circuit comprising:

• A. a substrate;
• B. functional combinational circuits formed on the substrate, the combinational circuits having plural functional registers that are converted to serially connected scan cells in a test mode of operation, there being a first number of scan cells;
• C. a second number of serial scan paths formed, on the substrate, of the serially connected scan cells, each scan path having a serial scan input and a serial scan output, the scan paths being connected in parallel with each serial scan input being connected to a serial input and with each serial scan output being selectively connected to a serial output, the number of scan cells in each scan path being equal and the number of scan cells in each scan path being substantially the first number of scan cells divided by the second number of scan paths;
• and
• D. a scan path control circuit having a plurality of separate control output leads, each separate control output lead being connected to one of the plurality of scan paths, the scan path control circuit outputs control signals to the plurality of scan paths, such that only one scan path is active at a time to input and output test data from the scan inputs and scan outputs.