Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times

A switching circuit for coupling a first terminal to a second terminal in response to the logic states of n clock signals, the switching circuit comprising an n x n array of switches having the switches of a row coupled in series between the first and second terminals, each switch of a row coupled to receive one of the n clock signals and, when coupling the first terminal to the second terminal, only one row of the array of switches having an activation sequence where the nth switch is activated subsequent to all other switches in the row.

A switching circuit for coupling a first terminal to a second terminal, comprising a plurality of rows, each row having a plurality of switches coupled in series between the first and second terminal, each switch in a row coupled to receive a respective clock signal and activate in response thereto, each row of switches having an activation sequence different from any other row and only one row having a sequence wherein the last switch in the row activates last when coupling the first terminal to the second terminal.

A method for controlling an array of transfer gates, the array including N rows and N columns, and each row having N transfer gates connected in series between first and second signal terminals, the method comprising:

• providing N clock signals to the array, each clock signal being provided to only one transfer gate in each row and only one transfer gate in each column;
• and
• activating the N clock signals to couple the first signal terminal to the second signal terminal.

A method for controlling an array of transfer gates, the array including N rows and N columns, and each row having N transfer gates connected in series between first and second signal terminals, the method comprising:

• providing N clock signals to the array, each transfer gate receiving one of the clock signals;
• and
• activating the N clock signals to activate the transfer gates of the array, each row of transfer gates activated according to a sequence to couple the first signal terminal to the second signal terminal such that in one row the Nth transfer gate is activated after the other transfer gates of the row have been activated.

A method for controlling an array of transfer gates to electrically couple first and second signal terminals, the array including N rows and N columns, and each row having N transfer gates series connected between the first and second signal terminals, the method comprising the steps of:

• providing N clock signals to the array, each clock signal being provided to only one transfer gate in each row and only one transfer gate in each column;
• and
• activating the N clock signals to activate the transfer gates of each row in accordance with a different transfer gate activation sequence to couple the first signal terminal to the second signal terminal.

A method for controlling an array of transfer gates to electrically couple first and second signal terminals, the array including N rows and N columns, and each row having N transfer gates connected in series between the first and second signal terminals, the method comprising the steps of:

• providing N clock signals to the array, each transfer gate receiving one of the clock signals;
• and
• activating the N clock signals to couple the first signal terminal to the second signal terminal, the sequence of transfer gate activation for each row being different.