Microprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputs

A microprocessor, comprising:

• a cache memory;
• and
• an arithmetic and logic unit containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
• first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, and
• combinatorial boolean logic that employs said intermediate bits to generate said carry out bit, said combinatorial boolean logic having first, second and third AND gates and first and second OR gates, wherein said second OR gate is coupled to outputs of said first, second and third AND gates, and an output of said first OR gate is coupled to an input of said second AND gate.

A microprocessor, comprising:

• a cache memory;
• and
• an arithmetic and logic unit containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
• first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, each of said first, second and third threshold logic gates having:
• a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at said at least two binary inputs, and
• a quantizer, coupled to said summer, that generates an output binary digit at a binary output thereof that is a function of said weighted sum;
• and combinatorial boolean logic that employs said intermediate bits to generate said carry out bit.

A digital signal processor, comprising:

• a signal input;
• a signal output;
• and
• a signal transformation unit employing said signal input to generate said signal output and containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
• first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, said first threshold logic gate generates a first intermediate bit based on a comparison between a concatenation of said second addend and augend bits and zero, and
• combinatorial boolean logic that employs said intermediate bits to generate said carry out bit.

A digital signal processor, comprising:

• a signal input;
• a signal output;
• and
• a signal transformation unit employing said signal input to generate said signal output and containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
• first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, and
• combinatorial boolean logic that employs said intermediate bits to generate said carry out bit, said combinatorial boolean logic comprises first, second and third AND gates and first and second OR gates, wherein said second OR gate is coupled to outputs of said first, second and third AND gates, and an output of said first OR gate is coupled to an input of said second AND gate.

A digital signal processor, comprising:

• a signal input;
• a signal output;
• and
• a signal transformation unit employing said signal input to generate said signal output and containing at least one of an adder and a multiplier, said at least one including a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, including:
• first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, each of said first, second and third threshold logic gates having:
• a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at said at least two binary inputs, and
• a quantizer, coupled to said summer, that generates an output binary digit at a binary output thereof that is a function of said weighted sum;
• and
• combinatorial boolean logic that employs said intermediate bits to generate said carry out bit.