# US 6,515,962 B1 · Hit-less switching pointer aligner apparatus and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 6,515,962 B1 - Document ID: US6515962B1 - Status: Granted - Kind: B1 - Application number: 09/354,865 - Filed: 1999-07-16 - Granted: 2003-02-04 - Earliest claimed: 1999-07-16 - Assignees: Alcatel - Inventors: David C. Sawey; Edmund K. Cher - Web page: https://patentgrep.com/patent/US6515962B1 ## CPC - H04B 10/032: using working and protection systems {(H04J14/0287 takes precedence)} - H04B 1/74: for increasing reliability, e.g. using redundant or spare channels or apparatus {(replacing by standby devices for amplifiers H03F1/52, H03F1/542)} - H04J 3/0623: {Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process} - H04L 1/06: using space diversity - H04J 2203/006: Fault tolerance and recovery - H04B: TRANSMISSION - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A system and method are disclosed for processing digital signals in a telecommunications system that allow for hit-less switching between a first digital signal in which a first payload, a first pointer value, and a first frame are transported on a first channel, and a second digital signal in which a second payload identical to the first payload, a second pointer value, and a second frame are transported on a second channel. The present invention includes first and second pointer followers, first and second comparators, a delay buffer with control circuit, first, second, third and fourth multiplexers, and a pointer generator. The delay buffer control circuit further comprises a write counter, a read counter, a phase detector, and a leak-out mechanism for reinitializing the delay buffer. The present invention aligns the payloads of the first and second digital signals to allow for hit-less selection between them. ## Claims ### Claim 1 A system for processing digital signals in a telecommunications system that allows for hit-less switching between a first digital signal, having a first payload, a first pointer value, and a first frame, that is transported on a first channel, and a second digital signal, having a second payload identical to the first payload, a second pointer value, and a second frame, that is transported on a second channel comprising: a first pointer follower to receive the first signal and forward the first pointer value and the first payload; a second pointer follower to receive the second signal and forward the second pointer value and the second payload; a first comparator to determine between the first signal and the second signal which signal is ahead and which is behind and to generate a select bit; a first multiplexer to receive the select bit, the first signal and the second signal and to select and forward the behind signal; a second multiplexer to receive the select bit, the first payload and the second payload, to determine which one of the first payload or the second payload corresponds to the ahead signal, and to select and forward the ahead signal payload; a third multiplexer to receive the select bit, the first pointer value and the second pointer value and to select and forward a bypass pointer value equal to the behind signal pointer value; a delay buffer with control circuit to receive, delay and forward the ahead signal payload; a pointer generator to receive the ahead signal payload, to generate a third frame and a PG pointer value, to forward the PG pointer value, and to include the third frame and the PG pointer value with the ahead signal payload to create and forward a third signal; a second comparator to receive the PG pointer value and the bypass pointer value and to generate, based on the amount of delay between the first payload and the second payload, an increment/decrement request signal used by the delay buffer to align the third signal with the behind signal; and a fourth multiplexer to receive the third signal and the behind signal, to hit-lessly select between the third signal and the behind signal, and to forward the selected signal. ### Claim 2 (depends on 1) The system of claim 1, wherein the third signal further comprises a third payload identical to the first and second payloads and wherein the third frame is aligned with the behind signal frame. ### Claim 3 (depends on 1) The system of claim 1, wherein the first digital signal and the second digital signal are frame-aligned with one another when received at the first pointer follower and at the second pointer follower, respectively. ### Claim 4 (depends on 1) The system of claim 1, wherein the first digital signal and the second digital signal have a format in which a signal payload and a pointer value can float within a signal frame. ### Claim 5 (depends on 1) The system of claim 1, further comprising a fifth multiplexer and a sixth multiplexer to each receive the third signal, the behind signal, and the select bit, and to each select, based on the select bit, only one of the third signal or the behind signal to return the behind signal to its original channel if necessary. ### Claim 6 (depends on 1) The system of claim 1, wherein the first, second and third multiplexers make their selection based on the value of the select bit. ### Claim 7 (depends on 1) The system of claim 1, wherein the first digital signal and the second digital signal have a SONET signal format. ### Claim 8 (depends on 1) The system of claim 1, wherein the delay buffer control circuit further comprises: a write counter in communication with the delay buffer to write the ahead payload into the delay buffer; a read counter in communication with the delay buffer to read the ahead payload from the delay buffer; and a phase detector to measure the offset between the write counter and the read counter, to generate a spill prevent signal, and to forward the spill prevent signal to the pointer generator to keep the delay buffer from spilling. ### Claim 9 (depends on 8) The system of claim 8, wherein the delay buffer control circuit further comprises a leaking mechanism to return the delay buffer to its nominal position following a cross-over where the ahead signal becomes a behind signal, or vice-versa. ### Claim 10 (depends on 1) The system of claim 1, wherein the first signal is further comprised of a first series of frames in which a first series of payloads and a first series of pointer values are being transported on the first channel, and wherein the second signal is further comprised of a second series of frames in which a second series of payloads identical to the first series of payloads and a second series of pointer values are being transported on the second channel. ### Claim 11 (depends on 10) The system of claim 10, wherein the second series of overheads have starting locations, for particular ones of the second series of frames, that can be different from the starting locations of identical particular frames in the first series of frames. ### Claim 12 (depends on 1) The system of claim 1, wherein the delay buffer is sized to compensate for the maximum anticipated offset between the first payload and the second payload. ### Claim 13 A method for processing digital signals in a telecommunications system that allows for hit-less switching between a first digital signal having a first payload, a first pointer value, and a first frame, that is transported on a first channel, and a second digital signal having a second payload identical to the first payload, a second pointer value, and a second frame, that is transported on a second channel, comprising: receiving the first signal at a first pointer follower and forwarding the first pointer value and the first payload; receiving the second signal at a second pointer follower and forwarding the second pointer value and the second payload; at a first comparator, determining between the first signal and the second signal which signal is ahead and which is behind and generating a select bit; receiving the ahead signal, the behind signal, and the select bit at a first multiplexer, and selecting and forwarding the behind signal; receiving the first payload, the second payload, and the select bit at a second multiplexer, and selecting and forwarding an ahead payload; receiving the first pointer value, the second pointer value, and the select bit at a third multiplexer, and selecting and forwarding a bypass pointer value; receiving the ahead payload at a delay buffer with control circuit and forwarding the ahead payload; aligning the ahead signal payload with the behind signal payload, comprising: (a) receiving at a pointer generator the ahead payload, generating a third frame and a PG pointer value, forwarding the PG pointer value, and including the third frame and the PG pointer value with the ahead payload to create a third signal; (b) comparing at a second comparator the PG pointer value and the bypass pointer value to determine the delay between the first payload and the second payload; (c) generating an increment/decrement request signal for the delay buffer to align the third signal with the behind signal; and (d) repeating steps (a)-(c) until the bypass pointer value is aligned with the PG pointer value; forwarding the third signal to a fourth multiplexer; and receiving at the fourth multiplexer the third signal and the behind signal, hit-lessly selecting between the third signal and the behind signal, and forwarding the selected signal to the rest of the telecommunications system. ### Claim 14 (depends on 13) The method of claim 13, wherein the third signal further comprises a third payload identical to the first and second payloads and wherein the third frame is aligned with the behind signal frame. ### Claim 15 (depends on 13) The method of claim 13, wherein the first digital signal and the second digital signal are frame-aligned with one another when received at the first pointer follower and at the second pointer follower, respectively. ### Claim 16 (depends on 13) The method of claim 13, wherein the first digital signal and the second digital signal have a format in which a signal payload and a pointer value can float within a signal frame. ### Claim 17 (depends on 13) The method of claim 13, further comprising the step of receiving at a fifth multiplexer and at a sixth multiplexer the third signal, the behind signal, and the select bit, and selecting at each of the fifth multiplexer and the sixth multiplexer, based on the select bit, only one of the third signal or the behind signal to return the behind signal to its original channel if necessary. ### Claim 18 (depends on 13) The method of claim 13, wherein the first, second and third multiplexers make their selection based on the value of the select bit. ### Claim 19 (depends on 13) The method of claim 13, wherein the first digital signal and the second digital signal have a SONET signal format. ### Claim 20 (depends on 13) The method of claim 13, wherein the delay buffer control circuit further comprises: a write counter in communication with the delay buffer to write the ahead payload into the delay buffer; a read counter in communication with the delay buffer to read the ahead payload from the delay buffer; and a phase detector to measure the offset between the write counter and the read counter, to generate a spill prevent signal, and to forward the spill prevent request signal to the pointer generator to keep the delay buffer from spilling. ### Claim 21 (depends on 20) The method of claim 20, wherein the delay buffer control circuit further comprises a leaking mechanism to return the delay buffer to its nominal position following a cross-over where the ahead signal becomes a behind signal, or vice-versa. ### Claim 22 (depends on 13) The method of claim 13, wherein the first signal is further comprised of a first series of frames in which a first series of payloads and a first series of pointer values are being transported on the first channel, and wherein the second signal is further comprised of a second series of frames in which a second series of payloads identical to the first series of payloads and a second series of pointer values are being transported on the second channel. ### Claim 23 (depends on 22) The method of claim 22, wherein the second series of overheads have starting locations, for particular ones of the second series of frames, that can be different from the starting locations of identical particular frames in the first series of frames. ### Claim 24 (depends on 13) The method of claim 13, wherein the delay buffer is sized to compensate for the maximum anticipated offset between the first payload and the second payload.