High sensitivity common source amplifier MRAM cell, memory array and read/write scheme

A magnetic memory comprising:

• a plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, each of the plurality of memory cells including a magnetic tunneling junction and a transistor having a source, a drain and a gate, the source of the transistor being coupled to the magnetic tunneling junction, the drain of the transistor being coupled with an output for reading the magnetic memory cell, the magnetic tunneling junction being configured to be written to a plurality of times;
• a plurality of row lines coupled to the plurality of rows, the plurality of row lines coupled to gate of the transistor in each of the plurality of memory cells in the plurality of rows;
• a row selector coupled to the plurality of row lines for selecting between the plurality of row lines and providing a constant voltage to a selected row of the plurality of rows.

A method for utilizing a magnetic memory comprising the steps of:

• (a) in a write mode, writing to a first portion of a plurality of memory cells, the plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, each of the plurality of memory cells including a magnetic tunneling junction and a transistor having a source, a drain and a gate, the source of the transistor being coupled to the magnetic tunneling junction, the drain of the transistor being coupled with an output for reading the magnetic memory cell, the write mode capable of writing to the first portion of the plurality of memory cells a plurality of times;
• (b) in a read mode, reading from a second portion of the plurality of memory cells.