US 6,510,976 B2Granted

Method for forming a flip chip semiconductor package

AssigneeAdvanpack Solutions Pte Ltd.

InventorsTan Kim Hwee, Romeo Emmanuel P. Alvarez

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Abstract

An oxidized (220) copper leadframe and a semiconductor die with copper posts extending from die pads, and with solder balls coated (225) with flux on the end of the copper posts, are provided. The semiconductor die is placed (230) on the oxidized copper leadframe, with the solder balls abutting portions of the layer of oxide, above and aligned with, interconnect locations on the leadframe. When reflowed (235), the flux on the abutting portions of the oxide layer selectively cleans these portions of the oxide layer, away from the interconnect locations. In addition, the solder balls change to molten state and adhere to the cleaned copper surfaces at the interconnect locations. Advantageously, the rest of the oxide layer that is not cleaned away provides a passivation layer that advantageously contains and prevents the molten solder from flowing away from the interconnect locations.

Claims41

Dependent claims

A method for forming a flip chip semiconductor package, the method comprising the steps of:

a) providing a patterned layer of metal conductors having a first surface, wherein the first surface has a pattern of interconnect locations thereon;
b) forming a layer of passivation on the first surface of the patterned layer of metal conductors;
c) providing a semiconductor die having a first surface with a pattern of pads thereon, wherein reflowable conductive deposits are disposed on the pads;
d) selectively disposing a passivation cleaner;
e) placing the semiconductor die on the patterned layer of metal conductors to form an assembly, wherein the reflowable conductive deposits abut portions of the layer of passivation, wherein the reflowable conductive deposits are adjacent the pattern of interconnect locations, and wherein the passivation cleaner adheres to the reflowable conductive deposits and the portions of the layer of passivation;
and
f) reflowing the assembly, wherein the passivation cleaner substantially removes the portions of the layer of passivation from the patterned layer of metal conductors, and wherein the reflowable conductive deposits form conductive interconnects between the pads on the semiconductor die and the interconnect locations on the patterned layer of metal conductors.

4 more elements

A method for forming a flip chip semiconductor package, the method comprising the steps of:

a) providing a patterned layer of metal conductors having a first surface, wherein the first surface has a pattern of interconnect locations thereon;
b) forming a layer of passivation on the first surface of the patterned layer of metal conductors;
c) providing a semiconductor die having a first surface with a pattern of pads thereon, wherein electrical conductors extend from the pads, and wherein solder deposits are disposed on free ends of the electrical conductors;
d) selectively disposing flux;
e) placing the semiconductor die on the patterned layer of metal conductors to form an assembly, wherein the solder deposits abut portions of the layer of passivation, wherein the solder deposits are adjacent the pattern of interconnect locations, and wherein the flux adheres to the solder deposits and the portions of the layer of passivation;
and
f) reflowing the assembly, wherein the flux substantially removes the portions of the layer of passivation from the patterned layer of metal conductors, wherein the solder deposits form solder interconnects between the electrical conductors on the semiconductor die and the interconnect locations on the patterned layer of metal conductors, and wherein the layer of passivation vaporizes and provides passivation while vaporizing.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/861,020Filed 18 May 2001
Published: US 2002/0170942 A121 Nov 2002
Granted: 28 Jan 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

B23K 1/206
Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating: cleaning
H10W 70/453
Leadframes: comprising flexible metallic tapes
H10W 70/458
Materials: of insulating layers on leadframes
H10W 72/20
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps