Method of fabricating a high-voltage transistor

A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

• forming a well region of a first conductivity type in a substrate of a second conductivity type;
• implanting a first dopant in the well region to form a first buried layer of the second conductivity type;
• forming an epitaxial layer of the first conductivity type on an upper surface of the substrate;
• implanting a second dopant in the epitaxial layer to form a second buried layer of the second conductivity type.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• successively implanting ions in a laterally extended region and a source region of a first epitaxial layer having a first conductivity type, each implant being performed at a different energy to form a first plurality of buried layers in the laterally extended region and a second plurality of buried layers in the source region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the first epitaxial layer such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the first epitaxial layer;
• forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer;
• successively implanting ions in a laterally extended region and a source region of the second epitaxial layer, each implant being performed at a different energy to form a third plurality of buried layers in the laterally extended region and a fourth plurality of buried layers in the source region, each of the third plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the second epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the second epitaxial layer;
• forming a gate insulated from the second epitaxial layer by a dielectric layer;
• forming a body region of the second conductivity type, the body region adjoining the dielectric layer;
• forming a source diffusion region of the first conductivity type in the body region;
• and
• forming a drain diffusion region of the first conductivity type in the second epitaxial layer.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• successively implanting ions in a laterally extended region of a first epitaxial layer having a first conductivity type, each implant being performed at a different energy to form a first plurality of buried layers in the laterally extended region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the first epitaxial layer such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the first epitaxial layer;
• forming a second epitaxial layer of the first conductivity type on the upper surface of the first epitaxial layer;
• successively implanting ions in a laterally extended region of the second epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the laterally extended region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the second epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the second epitaxial layer;
• forming a gate insulated from the second epitaxial layer by a dielectric layer;
• forming a body region of the second conductivity type adjoining the dielectric layer;
• forming a source diffusion region of the first conductivity type in the body region;
• and
• forming a drain diffusion region of the first conductivity type in the second epitaxial layer.

A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

• forming a first epitaxial layer of a first conductivity type on a substrate of a second conductivity type;
• successively implanting a first dopant in the first epitaxial layer, each implant being performed at a different energy to form a first plurality of buried layers, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the first epitaxial layer such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the first epitaxial layer;
• forming an epitaxial layer of the first conductivity type on an upper surface of the first epitaxial layer;
• successively implanting a second dopant in the second epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers within the second epitaxial layer, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the second epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the second epitaxial layer.

A method of fabricating a high-voltage field-effect transistor (HVFET), comprising:

• forming a well region of a first conductivity type in a substrate of a second conductivity type;
• successively implanting a first dopant into the well region, each implant being performed at a different energy to form a first plurality of buried layers in the well region;
• forming an epitaxial layer of the first conductivity type on the substrate;
• successively implanting a second dopant in a laterally extended region and a source region of the epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the laterally extended region and a third plurality of buried layers in the source region;
• forming a gate insulated from the epitaxial layer by a dielectric layer;
• forming a source diffusion region of the first conductivity type;
• and
• forming a drain diffusion region of the first conductivity type.

A method of fabricating a high-voltage field-effect transistor (HVFET), comprising:

• forming a well region of a first conductivity type on a substrate of a second conductivity type;
• successively implanting ions in the well region, each implant being performed at a different energy to form a first plurality of buried layers, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the substrate such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed in the well region;
• forming an epitaxial layer of the first conductivity type on the substrate;
• successively implanting ions in a laterally extended region of the epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the laterally extended region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the laterally extended region of the epitaxial layer;
• forming a gate insulated from the epitaxial layer by a dielectric layer, the gate extending over the upper surface adjacent the laterally extended region of the epitaxial layer;
• forming a source diffusion region of the first conductivity type in the body region;
• and
• forming a drain diffusion region of the first conductivity type in the epitaxial layer.

A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

• forming a well region of a first conductivity type in a substrate of a second conductivity type;
• successively implanting a first dopant in the well region, each implant being performed at a different energy to form a first plurality of buried layers in the well region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the substrate such that a corresponding first plurality of JFET conduction channels of the first conductivity type are formed;
• forming an epitaxial layer of the first conductivity type on the upper surface of the substrate;
• successively implanting ions a second dopant in the epitaxial layer, each implant being performed at a different energy to form a second plurality of buried layers in the epitaxial layer, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth relative to an upper surface of the epitaxial layer such that a corresponding second plurality of JFET conduction channels of the first conductivity type are formed in the epitaxial layer.