Programmatic synthesis of processor element arrays
AssigneeHewlett-Packard Company
InventorsRobert S. Schreiber, B. Ramakrishna Rau, Shail Aditya Gupta, Vinod K. Kathail, Sadun Anik
Life of this patent
Estimating the term…
Abstract
A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.
Claims27
A programmatic method for transforming a nested loop into a set of parallel processes for synthesis into a parallel array of processor elements, the method comprising:
- obtaining the nested loop and a performance requirement for executing the nested loop as parallel processes on the array of processor elements, where the nested loop has a loop body with one or more operations;
- based on a specified performance requirement, programmatically transforming the nested loop into parallel processes for synthesis into an array of processor elements, where each of the parallel processes corresponds to a set of iterations of the loop body, expressed as a single loop mapped to a processor element, and where each iteration is assigned a start time to initiate execution on the processor element;
- and
- generating code representing the transformed nested loop as a two dimensional loop in which a first dimension iterates over time and a second dimension iterates over processor elements.
A programmatic method for synthesizing a set of parallel processes, each comprising a single loop in parallel form, into a parallel array of processor elements, the method comprising:
- synthesizing a structural representation of a data path for a processor element that executes the single loop based on operations in the single loop;
- scheduling the operations in the single loop for execution in the data path so as to satisfy a specified processor cost or performance constraint;
- programmatically synthesizing an interconnect between functional units and local storage in the data path for each processor element;
- and
- programmatically replicating and interconnecting the processor elements into a parallel array that satisfies the processor cost or performance constraint.
A processor element array comprising:
- an array of processor elements, each having one or more functional units for executing operations, one or more registers for storing inputs and outputs of the operations, and an interconnect for connecting registers to functional units;
- the functional units supporting predicated execution of the operations and producing output for the operations as predicate-data pairs;
- and
- the interconnect using the predicates to control transfer of data from the functional units to corresponding registers.
Dependencies are inferred from the claim text.