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US 6,504,404 B2Granted
Semiconductor integrated circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHideki Uchiki, Harufusa Kondoh
Life of this patent
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Abstract
A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.
Claims15
A semiconductor integrated circuit comprising:
- a differential amplifier including a first MOS transistor having a gate terminal connected to a first node, a second MOS transistor having a gate terminal connected to a second node, and a third MOS transistor having a drain terminal connected to source terminals of the first and second MOS transistors respectively;
- a level detector circuit which detects an intermediate voltage level between voltages at the first and second nodes;
- and
- a bias generation circuit which generates a bias voltage to be applied to a gate terminal of the third MOS transistor in the differential amplifier based on the voltage level detected by the level detector circuit.
1 more element
A semiconductor integrated circuit comprising:
- a differential amplifier including a first MOS transistor having a gate terminal connected to a first node, a second MOS transistor having a gate terminal connected to a second node, and a third MOS transistor having a drain terminal connected to source terminals of the first and second MOS transistors respectively;
- a first element connected between the first node and a third node;
- a second element connected between the second node and the third node;
- and
- a bias generation circuit which generates a bias voltage to be applied to a gate terminal of the third MOS transistor in the differential amplifier based on a voltage level at the third node.
2 more elements
Dependencies are inferred from the claim text.