US 6,503,826 B1Granted

Semiconductor device and method for manufacturing the same

AssigneeNEC Corporation

InventorNoriaki Oda

Life of this patent

Estimating the term…

Loading patent…

Abstract

In an LDD structure MOSFET, a protecting multilayer insulating film is formed to cover a gate electrode in order to protect the gate electrode and the gate oxide film from a moisture included in an upper level layer. The protecting multilayer insulating film includes a protecting nitride film for preventing infiltration of moisture, and another protecting insulator film having a compressive stress for relaxing a tensile stress of the protecting nitride film. Thus, it is possible to prevent infiltration of moisture, and simultaneously, it is possible to minimize energy levels for trapping electrons and holes, which would have otherwise been formed within the gate oxide film and at a boundary between the gate oxide film and the semiconductor substrate because of the tensile stress of the protecting nitride film.

Claims9

Dependent claims

A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator film on a semiconductor substrate of a first conductivity type to define a device region;
forming a gate insulator film on said semiconductor substrate within said device region;
forming a gate electrode on said gate insulator film within said device region;
forming a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment by using said gate electrode as a mask;
forming a sidewall insulator film on a side wall of said gate electrode;
forming a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment by using said sidewall insulator film and said gate electrode as a mask;
forming a protecting insulating film having at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film;
and
forming an interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection formed on said interlayer insulator film,
wherein the step of forming said protecting insulating film includes the steps of depositing a first oxide film having a thickness of 90 nm to 110 nm on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film by an atmospheric pressure chemical vapor deposition process,
succeedingly depositing a nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and
thereafter, depositing a second oxide film having a thickness of 40 nm to 60 nm by a plasma chemical vapor deposition process.

9 more elements

A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator film on a semiconductor substrate of a first conductivity type to define a device region;
forming a gate insulator film on said semiconductor substrate within said device region;
forming a gate electrode on said gate insulator film within said device region;
forming a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment by using said gate electrode as a mask;
forming a sidewall insulator film on a side wall of said gate electrode;
forming a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment by using said sidewall insulator film and said gate electrode as a mask;
forming a protecting insulating film having at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film;
and
forming an interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection formed on said interlayer insulator film,
wherein the step of forming said protecting insulating film includes the steps of depositing a first nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and succeedingly depositing a second nitride film having a thickness of 30 nm to 100 nm by a plasma chemical vapor deposition process.

7 more elements

A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator film on a semiconductor substrate of a first conductivity type to define a device region;
forming a gate insulator film on said semiconductor substrate within said device region;
forming a gate electrode on said gate insulator film within said device region;
forming a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment by using said gate electrode as a mask;
forming a sidewall insulator film on a side wall of said gate electrode;
forming a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment by using said sidewall insulator film and said gate electrode as a mask;
forming a protecting insulating film having at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film;
and
forming an interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection formed on said interlayer insulator film,
wherein the steps of forming said protecting insulating film includes the step of depositing an oxide film having a thickness of 90 nm to 110 nm on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film by an atmospheric pressure chemical vapor deposition process,
succeedingly depositing a first nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and
thereafter, depositing a second nitride film having a thickness of 30 nm to 100 nm by a plasma chemical vapor deposition process.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/527,212Filed 16 Mar 2000 · division
Priority: JP 9-31066212 Nov 1997
Granted: 7 Jan 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10P 14/6923
The material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC: the material being boron or…
H10P 14/6334
Deposition from the gas or vapour phase: using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
H10P 14/6336
Using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition: in the presence of a plasma [PECVD]
H10P 14/662
Characterised by the type of materials: laminate layers, e.g. stacks of alternating high-k metal oxides