Adder circuit employing logic gates having discrete weighted inputs and a method of operation therewith
AssigneeRn2R, L.L.C.
InventorValeriu Beiu
Life of this patent
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Abstract
A circuit and method for deriving an adder output bit from adder input bits. In one embodiment, the circuit includes: (1) first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial boolean logic that generates the adder output bit from the intermediate bits.
Claims24
A circuit for deriving an adder output bit from adder input bits, comprising:
- first, second and third threshold gates that generate intermediate bits based on threshold comparisons of concatenations of said adder input bits;
- and
- combinatorial boolean logic that employs said intermediate bits to generate said adder output bit;
- wherein said combinatorial boolean logic comprises first and second AND gates and an OR gate coupled to outputs thereof.
A circuit for deriving an adder output bit from adder input bits, comprising:
- first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said adder input bits, each of said first, second and third logic threshold gates having:
- a summer, having at least two binary inputs with corresponding discrete weights, that generates a weighted sum of input binary digits presented at said at least two binary inputs, and
- a quantizer, coupled to said summer, that generates an output binary digit at a binary output thereof that is a function of said weighted sum;
- and
- combinatorial boolean logic that employs said intermediate bits to generate said adder output bit.
A method of deriving an adder output bit from adder input bits, comprising:
- generating intermediate bits based on threshold comparisons of concatenations of said adder input bits;
- and
- employing combinatorial boolean logic and said intermediate bits to generate said adder output bit;
- wherein said employing combinatorial boolean logic and said intermediate bits to generate said adder output bit is carried out by first and second AND gates and an OR gate coupled to outputs thereof.
A method of deriving an adder output bit from adder input bits, comprising:
- generating intermediate bits based on threshold comparisons of concatenations and said adder input bits, wherein said generating said intermediate bit comprises:
- generating a weighted sum of input binary digits presented at least two binary inputs, and
- generating an output binary digit at a binary output thereof that is a function of said weighted sum;
- and
- employing combinatorial boolean logic and said intermediate bits to generate said adder output bit.
A circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits, comprising:
- a first logic gate that generates a first intermediate bit based on a comparison between a concatenation of said second addend and augend bits and zero;
- a second logic gate that generates a second intermediate bit based on a comparison between said concatenation of said second addend and augend bits and two;
- a third logic gate that generates a third intermediate bit based on a comparison between a concatenation of said first addend and augend bits and said carry in bit and four;
- a first OR gate that generates a fourth intermediate bit based on said first addend and augend bits;
- a first AND gate that generates a fifth intermediate bit based on said first addend and augend bits;
- a second AND gate that generates a sixth intermediate bit based on said first and third intermediate bits;
- a third AND gate that generates a seventh intermediate bit based on said second and fourth intermediate bits;
- and
- a second OR gate that generates said carry out bit based on said sixth, seventh and fifth intermediate bits.
Dependencies are inferred from the claim text.