US 6,496,940 B1 · Multiple processor system with standby sparing

Abstract

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Claims10

Dependent claims

A multiple processing system, comprising:

N central processing units where N is an integer greater than or equal to 3, each central processing unit comprising a plurality of processors;
a plurality of input/output devices;
and
a network interconnecting each of the N central processing units and the input/output devices so that any one of the N central processing units has separate and independent communicative access to any one of the input/output devices, the network further providing interprocessor communication between the N central processing units, the network including a plurality of routing devices, at least one of the routing devices synchronizing communications for one of the central processing units to enable lockstep operation within said one of the central processing units;
whereby operational tasks of a failed one of the N central processing units employing a one of the input/output devices are performed by any of the other N central processing units including employment of the one of the input/output devices.

2 more elements

A multiple processing system, comprising:

N central processing units, including a first central processing unit and a second central processing unit and N being an integer greater than 2, each central processing unit comprising a plurality of processors, each of the N central processing units operating to execute one or more processes;
a primary process executing on the first central processing unit;
a backup process associated with the second central processing unit, the backup process being substantially identical in operation and function to the primary process;
a plurality of input/output devices;
and
a network interconnecting the N central processing units and the plurality of input/output devices so that any one of the N central processing units has separate and independent communicative access to any one of the input/output devices, the network further providing interprocessor communication between the N central processing units, the network including a plurality of routing devices, at least one of the routing devices synchronizing communications for one of the central processing units to enable lockstep operation within said one of the central processing units.

3 more elements

Dependencies are inferred from the claim text.

Multiple processor system with standby sparing

Life of this patent

Multiple processor system with standby sparing

Life of this patent

Abstract

Claims10