Method and integrated circuit for bit line soft programming (BLISP)
AssigneeMacronix International Co., Ltd.
InventorsTzeng-Huei Shiau, Ray-Lin Wan, Han Sung Chen, Yu-Shen Lin, Wen-Pin Lu, Tso-Ming Chang
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AssigneeMacronix International Co., Ltd.
InventorsTzeng-Huei Shiau, Ray-Lin Wan, Han Sung Chen, Yu-Shen Lin, Wen-Pin Lu, Tso-Ming Chang
Estimating the term…
A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines. The defective bit lines in the first memory array can be disabled during the soft program and replaced by corresponding redundant bit lines disposed in the second memory array, so that the soft program is not applied to the defective bit lines. By preventing application of the soft program to the defective bit lines, the BLISP method avoids consumption of excessive current that would otherwise be consumed by very low threshold voltage memory cells disposed on the defective bit lines. The excessive current would render the soft program method much less efficient.
In a floating gate integrated circuit having a first memory array including a plurality of bit lines identified by bit line addresses, the bit lines coupled to floating gate memory cells configured to be programmed and erased, wherein each of the cells has a drain, a source, and a control gate, and wherein the control gates of the cells are in communication with word lines, a method for soft programing floating gate memory cells comprising:
In a floating gate integrated circuit having a first memory array including a plurality of bit lines, the bit lines corresponding to floating gate memory cells configured to be programmed and erased, wherein each of the cells has a drain, a source, and a control gate, and wherein the control gates of the cells are in communication with word lines, a method for soft programming floating gate memory cells comprising:
Dependencies are inferred from the claim text.