Memory architecture and addressing for optimized density in integrated circuit package or on circuit board

A memory module comprising:

• a plurality of X memory circuits, wherein at least one of the memory circuits includes a size D1 a first dimension, and a plurality of N memory N memory blocks, each of the memory block including a size B1 in the first dimension, wherein each of the memory circuits is carried in an area of a carrier, the area of a carrier, the area having a size C1 in the first dimension, wherein (C1-D1) is less than B1, and N is not an even power of two;
• and
• a memory controller connected to each of the memory circuits, wherein the memory controller decodes a plurality of address bits to select a select line to access the memory circuit.

A method comprising:

• forming a memory circuit including a size D1 in a first dimension, and a plurality of N memory blocks, each of the memory block including a size B1 in the first dimension;
• and
• mounting the memory circuit on a carrier having an area for carrying the memory circuit, the area having a size C1 in the first dimension, wherein (C1-D1) is less than B1, and N is not an even power of two.

A method comprising:

• decoding a plurality of address bits to produce a selected decode line among a plurality of N decode lines;
• and
• accessing a memory block among a plurality of N memory blocks of a memory circuit based on the selected decode line, wherein the memory circuit includes a size D1 in a first dimension, and each of the memory block including a size B1 in the first dimension, and wherein each of the memory circuits is disposed on an area of a carrier, the area having a size C1 in the first dimension, wherein (C1-D1) is less than B1, and N is not an even power of two.

A method comprising:

• receiving a plurality of address bits;
• and
• decoding the address bits to access a memory circuit of a memory module, wherein the memory module includes at least two of the memory circuits, wherein each of the memory circuit includes a size D1 in a first dimension, and a plurality of N memory blocks, each of the memory block including a size B1 in the first dimension, and wherein each of the memory circuits is disposed on an area of a carrier, the area having size C1 in the first dimension, wherein (C1-D1) is less than B1, and N is not an even power of two.