Programmable logic arrays with ultra thin body transistors

A programmable logic array, comprising:

• a plurality of input lines for receiving an input signal;
• a plurality of output lines;
• and
• one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
• an ultra thin single crystalline vertical first source/drain region;
• an ultra thin single crystalline vertical second source/drain region;
• an ultra thin single crystalline vertical body region, disposed alongside an oxide pillar, and which couples the first and the second source/drain regions;
• and
• wherein a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions is much less than a vertical length of the ultra thin single crystalline vertical body region.

A programmable logic array, comprising:

• a plurality of input lines for receiving an input signal;
• a plurality of output lines;
• and
• one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
• a number of vertical pillars extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a number of single crystalline ultra thin vertical transistor that are disposed adjacent the number of vertical pillars, wherein each single crystalline vertical transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

A programmable logic array, comprising:

• a plurality of input lines for receiving an input signal;
• a plurality of output lines;
• and
• one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
• a number of vertical pillars extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical transistors formed along opposing sides of each pillar, wherein each single crystalline vertical transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• and
• wherein a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;
• a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array;
• and
• wherein each of the number of input lines is disposed in a trench between rows of the pillars for addressing the ultra thin single crystalline vertical body regions of the single crystalline vertical transistors that are adjacent to the trench.

A low voltage programmable logic array, comprising:

• a number of input lines for receiving an input signal;
• a number of output lines;
• and a first logic plane that receives a number of input signals on the number of input lines, the first logic plane having a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• a second logic plane coupled to the first logic plane by a number of interconnect lines, the second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function;
• wherein each logic cell includes:
• a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• and
• a number of single crystalline ultra thin vertical transistors formed along selected sides of each pillar, wherein each single crystalline vertical transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• and
• a gate opposing the vertical body region and separated therefrom by a gate oxide;
• a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array.

An electronic system, comprising:

• a memory;
• a processor coupled to the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
• and
• wherein each of the logic cells includes;
• a vertical pillar extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• and
• at least one single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar, wherein each single crystalline vertical transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

An electronic system, comprising:

• a memory;
• a processor coupled to the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
• an ultra thin single crystalline vertical first source/drain region;
• an ultra thin single crystalline vertical second source/drain region;
• an ultra thin single crystalline vertical body region, disposed alongside an oxide pillar, and which couples the first and the second source/drain regions;
• and
• wherein a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions is much less than a vertical length of the ultra thin single crystalline vertical body region.

An electronic system, comprising:

• a memory;
• a processor coupled to the memory;
• and
• wherein the processor includes at least one programmable logic array including:
• a number of input lines for receiving an input signal;
• a number of output lines;
• and
• one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a number of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes:
• a number of vertical pillars extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• and
• a number of single crystalline ultra thin vertical transistor that are disposed adjacent the number of vertical pillars, wherein each single crystalline vertical transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

An electronic system, comprising:

• a memory;
• a processor coupled to the memory;
• and
• wherein at least one of the processor and memory include a programmable logic array including:
• a number of input lines for receiving an input signal;
• a number of output lines;
• a first logic plane that receives a number of input signals on the number of input lines, the first logic plane having a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• a second logic plane coupled to the first logic plane by a number of interconnect lines, the second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function;
• wherein each logic cell includes:
• a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• and
• a number of single crystalline ultra thin vertical transistors formed along selected sides of each pillar, wherein each single crystalline vertical transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• and
• a gate opposing the vertical body region and separated therefrom by a gate oxide;
• a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array.

A method for forming a programmable logic array, comprising:

• forming a first logic plane that receives a number of input signals, wherein forming the first logic plane includes forming a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• forming a second logic plane, wherein forming the second logic plane includes forming a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function;
• and
• wherein forming each of the logic cells includes;
• forming a vertical pillar extending outwardly from a semiconductor substrate, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer of a first conductivity type separated by an oxide layer;
• and
• forming a single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar, wherein forming the single crystalline vertical transistor includes;
• depositing a lightly doped polysilicon layer of a second conductivity type over the pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
• annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
• and
• wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by a body region formed of the single crystalline vertically oriented material of the second conductivity type.

A method for forming a programmable logic array, comprising:

• forming a plurality of input lines for receiving an input signal;
• forming a plurality of output lines;
• and
• forming one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein forming the first logic plane and the second logic plane forming a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein forming each logic cell includes:
• forming an ultra thin single crystalline vertical first source/drain region;
• forming an ultra thin single crystalline vertical second source/drain region;
• forming an ultra thin single crystalline vertical body region disposed alongside an oxide pillar and which couples the first and the second source/drain regions;
• and
• wherein forming each logic cell includes forming a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions which is much less than a vertical length of the ultra thin single crystalline vertical body region.

A method for forming a programmable logic array, comprising:

• forming a plurality of input lines for receiving an input signal;
• forming a plurality of output lines;
• and
• forming one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein forming the first logic plane and the second logic plane includes forming a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein forming each logic cell includes:
• forming a pillar extending outwardly from a semiconductor substrate, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• and
• forming a single crystalline ultra thin vertical transistor which is disposed adjacent the vertical pillar, wherein forming the single crystalline vertical transistor includes;
• depositing a lightly doped polysilicon layer of a second conductivity type over each pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
• annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
• and
• wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by a body region formed of the single crystalline vertically oriented material of the second conductivity type.

A method of forming a low voltage programmable logic array, comprising:

• forming a number of input lines for receiving an input signal;
• forming a number of output lines;
• forming a first logic plane that receives a number of input signals on the number of input lines, wherein forming the first logic plane includes forming a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs;
• forming a second logic plane coupled to the first logic plane by forming a number of interconnect lines, wherein forming the second logic plane includes forming a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function;
• wherein forming each logic cell includes;
• forming a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein forming each pillar includes forming a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• and
• forming a number of single crystalline ultra thin vertical transistors formed along selected sides of each pillar, wherein forming each single crystalline vertical transistor includes;
• depositing a lightly doped polysilicon layer of a second conductivity type over each pillar and directionally etching the polysilicon layer of the second conductivity type to leave only on sidewalls of the pillars;
• annealing the pillar such that the lightly doped polysilicon layer of the second conductivity type recrystallizes and lateral epitaxial solid phase regrowth occurs vertically to form a single crystalline vertically oriented material of the second conductivity type;
• and
• wherein the annealing causes the single crystalline first and second contact layers of a first conductivity type seed a growth of single crystalline material of the first conductivity type into the lightly doped polysilicon layer of the second type to form vertically oriented first and second source/drain regions of the first conductivity type separated by a body region formed of the single crystalline vertically oriented material of the second conductivity type;
• and
• forming a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array.