Circuit system suitable for codifying NRZ type binary signals into CMI type binary signals

A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals comprising:

• a presynchronization device which receives in input said NRZ type binary signals and an out-of-phase clock signal;
• a first bistable means which receives a synchronous clock signal and the output of said presynchronization device;
• a combinatory logic device which receives said NRZ type binary signals and the output of said first bistable means;
• a second bistable means which receives said synchronous clock signal and the output of said combinatory logic device;
• a third bistable means which receives said synchronous clock signal and the output of said presynchronization device;
• and
• an EXOR type logical gate which receives the outputs of said second and third bistable means and generates an output which is the input of said combinatory logic device, so as to determine an identical physical path for the codifying of the “1” bit and of the “0” bit, whether the transition is on the leading edges and/or trailing edges or at mid period (T), bits present in said NRZ type binary signals, so that the parameters set by the G703 ITU standard for the creation of said CMI type binary signals are complied with.