Data prefetch technique using prefetch cache, micro-TLB, and history file

A digital system comprising;

• a memory system;
• a bus coupled to the memory system;
• a processor coupled to the bus;
• and
• a data cache system coupled to the processor comprising:
• first and second cache memories;
• first and second translation lookaside buffers coupled to the first and second cache memories, respectively, wherein the first translation lookaside buffer provides an address translation to the first cache memory and the second translation buffer provides an address translation to the second cache memory;
• a first execution unit coupled to the first cache memory, the second cache memory and the first translation lookaside buffer;
• a second execution unit coupled to the second cache memory and the second translation lookaside buffer;
• and
• a prefetch logic block that selectively causes data to be loaded into the second cache memory prior to the data being referenced by a memory instruction.

A data cache system comprising:

• first and second cache memories;
• first and second translation lookaside buffers;
• a history file for storing historical information related to memory instructions;
• a first execution unit coupled to the first and second cache memories and the first translation lookaside buffer;
• and
• a second execution unit coupled to the second cache memory and the second translation lookaside buffer;
• a prefetch logic block for selectively loading data in the second cache memory prior to the data being referenced by a memory instruction;
• and
• a steering logic block for selectively steering the memory instruction to the second execution unit.

A data cache system comprising:

• a cache memory;
• a prefetch cache memory;
• a first execution pipeline coupled to the cache memory and the prefetch cache memory;
• a second execution pipeline coupled the prefetch cache memory;
• and
• a steering logic block coupled to the first execution pipeline and the second execution pipeline,
• wherein the steering logic block provides instructions to either the first execution pipeline or the second execution pipeline.

A data cache system comprising:

• a steering logic block configured to receive instructions, and further configured to determine if a first criteria is met for each instruction, to provide the instruction at a second port if the first criteria is met, and otherwise to provide the instruction to a first port;
• a first instruction pipeline configured to receive instructions from the first port of the steering logic block;
• a second instruction pipeline configured to receive instruction from the second port of the steering logic block;
• a data cache memory configured to receive addresses from the first instruction pipeline;
• and
• a prefetch cache memory configured to receive addresses from the first instruction pipeline and the second instruction pipeline.

A method of retrieving data from a cache system comprising:

• receiving instructions using a steering logic block;
• for each instruction, determining if a criteria is met, and providing the instruction to a second execution pipeline if the criteria is met, else providing the instruction to a first execution pipeline;
• receiving addresses from the first execution pipeline using a cache memory;
• and
• receiving addresses from the first execution pipeline and the second execution pipeline using a prefetch cache memory.