Shared FP and SIMD 3D multiplier

A method for performing integer and floating point multiplication, the method comprising:

• detecting a type of multiplication operation to be performed;
• asserting one or more control signals in response to detecting the type of multiplication operation to be performed;
• conveying the asserted control signals to a multiplier and selection logic configurable to perform the multiplication operation;
• selecting a multiplier operand and a multiplicand operand corresponding to the multiplication operation to be performed in response to the asserted control signals;
• multiplying the multiplier operand and the multiplicand operand, wherein the multiplication operation is selected from the group comprising:
• scalar floating point multiplication operations, iterative multiplication operations performed in the context of a divide operation, and iterative multiplication operations performed in the context of a square root operation;
• wherein multiplying includes:
• generating a plurality of partial products;
• summing the partial products using an adder tree to generate a sum component and a carry component;
• summing the sum component and the carry component assuming there is no overflow to generate a first result;
• summing the sum component and the carry component assuming there is an overflow to generate a second result;
• and
• selecting either the first result or the second result based on a most significant bit of either the first result or the second result.

A floating point unit comprising:

• a multiplier configured to perform scalar floating point multiplication of the form A×B,
• wherein the multiplier includes:
• a binary adder tree configured to generate a result having a sum component and a carry component;
• and
• an overflow adder coupled to the binary adder tree and configured to sum the sum component and the carry component from the adder tree with a first rounding constant assuming the resulting sum will be normalized and have an overflow;
• a non-overflow adder coupled to the binary adder tree and configured to sum the sum component and the carry component from the adder tree with a second rounding constant assuming the resulting sum will be normalized and not have an overflow;
• and
• a non-rounding adder coupled to the binary adder tree and configured to sum the sum component and the carry component from the adder tree assuming the result is not be rounded.

A computer system comprising:

• a processor;
• a main system memory coupled to the processor via a bus;
• wherein the processor includes a floating point unit including:
• a multiplier configured to perform floating point multiplication of the form A×B;
• a register configured to store results generated by the multiplier;
• and
• selection logic configured to select source operands for the multiplier to multiply,
• wherein the multiplier includes:
• a binary adder tree configured to generate a result having a sum component and a carry component;
• and
• an overflow adder coupled to the binary adder tree and configured to sum the sum component and the carry component from the adder tree with a first rounding constant assuming the resulting sum will be normalized and have an overflow;
• a non-overflow adder coupled to the binary adder tree and configured to sum the sum component and the carry component from the adder tree with a second rounding constant assuming the resulting sum will be normalized and not have an overflow;
• and
• a non-rounding adder coupled to the binary adder tree and configured to sum the sum component and the carry component from the adder tree assuming the result is not be rounded.