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US 6,490,188 B2Granted
Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
AssigneeMicron Technology, Inc.
InventorsJames P. Nuxoll, Steven L. Hamren
Life of this patent
Estimating the term…
Abstract
Disclosed are semiconductor devices having terminal arrangements in which mirrored pairs of the semiconductor devices can be tested by a common test device.
Claims16
A semiconductor chip set, comprising:
- a first semiconductor chip having a first plurality of terminals;
- and
- a second semiconductor chip having a second plurality of terminals, wherein
- said first and second semiconductor chips are a mirror pair, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
1 more element
A semiconductor chip, comprising:
- a first plurality of terminals, said semiconductor chip being one-half of a mirror pair of semiconductor chips, wherein the other half of said mirror pair is a second semiconductor chip having a second plurality of terminals, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
A memory module, comprising:
- a module board;
- and
- a semiconductor chip set coupled to said module board, said semiconductor chip set comprising:
- a first semiconductor chip having a first plurality of terminals;
- and
- a second semiconductor chip having a second plurality of terminals, wherein
- said first and second semiconductor chips are a mirror pair, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
4 more elements
A processor system comprising:
- a processor;
- and
- a module board electrically coupled to said processor, said module board comprising:
- a semiconductor chip set coupled to said module board, said semiconductor chip set comprising:
- a first semiconductor chip having a first plurality of terminals;
- and
- a second semiconductor chip having a second plurality of terminals, wherein
- said first and second semiconductor chips are a mirror pair, and wherein said first plurality of terminals has a function assignment arrangement identical to that of said second plurality of terminals such that said first and second semiconductor chips are configured to be tested by a single test device.
5 more elements
Dependencies are inferred from the claim text.