High performance multi-chip flip chip package
AssigneeFairchild Semiconductor Corporation
InventorRajeev Joshi
Life of this patent
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Abstract
A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.
Claims12
A multi-chip semiconductor package comprising:
- a base layer;
- a dielectric layer of laminating medium disposed over the base layer;
- a lead frame layer disposed over the dielectric layer, the lead frame layer having a plurality of cavities;
- a plurality of silicon dies attached inside the plurality of cavities and electrically coupled thereto, respectively, wherein each cavity is sized such that a surface of the silicon die attached therein and a surface of an edge of the lead frame layer adjacent to the silicon die form a substantially uniform plane;
- and
- an array of solder balls including an inner array distributed across the uniform plane disposed directly on the surface of each silicon die, and an outer array disposed directly on the surface of the edges of the lead frame layer adjacent to each silicon die.
A multi-chip semiconductor package comprising:
- a base layer;
- a dielectric layer of laminating medium disposed over the base layer;
- an electrically conductive lead frame layer disposed over the dielectric layer, the lead frame layer being physically divided into a plurality of electrically isolated lead frame sections, each section having a cavity;
- a plurality of silicon dies each having its substrate attached inside and making electrical contact with a respective cavity;
- and
- an inner array of solder balls distributed across an active surface of each of the plurality of silicon dies, and an outer array of solder balls disposed on a surface of cavity edges of the lead frame layers.
Dependencies are inferred from the claim text.