Dynamic code motion optimization and path tracing

A method of reordering instructions for execution on a processor comprising:

• providing a dynamic instruction trace;
• identifying some of the instructions in the dynamic instruction trace as barrier instructions;
• simulating the execution of the dynamic instruction trace;
• determining an instruction in the dynamic instruction trace that will cause the processor to stall;
• and
• hoisting a later instruction above the stalled instruction forming a reordered instruction trace, wherein the later instruction is not raised above the barrier instruction.

A method of reordering instructions for execution on a processor comprising:

• providing a dynamic instruction trace;
• identifying store instructions as barrier instructions;
• identifying branch instructions as barrier instruction;
• maintaining a count of registers needed for execution at a given point in time;
• and
• identifying instructions that cause the count to exceed a predetermined maximum value as a barrier instruction.
• simulating the execution of the dynamic instruction trace;
• determining an instruction in the dynamic instruction trace that will cause the processor to stall;
• and
• hoisting a later instruction above the stalled instruction forming a reordered instruction trace, wherein the later instruction is not raised above the barrier instructions.

A computer program product for execution on a computer system, comprising:

• code for providing a list of instructions with an initial execution order with early instructions scheduled to execute before later instructions;
• code for defining a subset of the instructions as barrier instructions;
• code for hoisting an instruction to an earlier position in the list of instructions, wherein the barrier instructions determine how early in the instruction list an instruction can be hoisted;
• code for maintaining a count of the number of registers needed to execute the list of instructions;
• code for determining whether hoisting the instruction will cause the count to exceed a predetermined register number;
• and
• if hoisting the instruction will exceed the predetermined register number, including the instruction in the subset of barrier instructions.

A computer system comprising:

• a processor for executing instructions;
• a bus coupled to the processor;
• a memory coupled to the bus;
• a computer program stored in the memory, the computer program comprising:
• code for providing a list of instructions with an initial execution order with early instructions scheduled to execute before later instructions;
• code for defining a subset of the instructions as barrier instructions;
• code for hoisting an instruction to an earlier position in the list of instructions, wherein the barrier instructions determine how early in the instruction list an instruction can be hoisted;
• code for maintaining a count of the number of registers needed to execute the list of instructions;
• code for determining whether hoisting the instruction will cause the count to exceed a predetermined register number;
• and
• if hoisting the instruction will exceed the predetermined register number, including the instruction in the subset of barrier instructions.