Hierarchical location constraints for programmable layouts

A method of hierarchially designating a target location in a programmable system for a circuit element to be implemented in the programmable system, the method comprising:

• designating a first level of hierarchy in the programmable system by identifying at least a first block of programmable logic at the first level of hierarchy;
• designating a second level of hierarchy within the first block, the second level of hierarchy including at least a third block of programmable logic;
• applying a first location constraint to the circuit element, the first location constraint uniquely identifying the first block within the programmable system, and further uniquely identifying the third block within the first block;
• dividing the first block into an array of tiles;
• applying a uniform coordinate system to the array of tiles;
• determining a set of coordinates for the third block according to the uniform coordinate system by determining the location of the third block within the array of tiles;
• and
• when applying the first location constraint, uniquely identifying the third block within the first block by referencing the set of coordinates.

A method of hierarchically designating a target location in a programmable system for a circuit element to be implemented in the programmable system, the method comprising:

• identifying a first block of programmable logic at the first level of hierarchy and assigning an identifier thereto;
• identifying third and fourth blocks of programmable logic within the first block and assigning different identifiers thereto;
• identifying a fifth block of programmable logic within the third block and assigning an identifier thereto;
• identifying a seventh block of programmable logic within the fourth block and assigning an identifier thereto, the seventh block having the same identifier as the fifth block;
• and
• applying a first location constraint to the circuit element, the first location constraint comprising the identifier assigned to the first block and the identifier assigned to the fifth and seventh blocks.

A method of designating a target logic block in a non-uniform programmable array of logic blocks, the method comprising:

• dividing the non-uniform programmable array into an array of tiles, with each logic block corresponding to one or more tiles;
• applying a uniform coordinate system to the array of tiles;
• determining a set of coordinates for the target logic block according to the uniform coordinate system by determining the location within the array of tiles of the one or more tiles corresponding to the target logic block;
• and
• applying a first location constraint to a circuit element to be implemented in the target logic block, the first location constraint identifying the target logic block by referencing the set of coordinates.