Layout design system of semiconductor ic device, layout design method of semiconductor ic device and computer-readable recording medium on which programs for allowing computer to execute respective means in the system or respective steps in the method are recorded

A layout design system of semiconductor IC device, comprising:

• a first design section which decides a first clock tree between a plurality of blocks based on a placement position of a clock buffer to be a basis of a clock signal in the blocks and based on a delay value of the clock signal propagated in the first clock tree and a size of each of the blocks, the first clock tree is designed so that a first clock skew in the first clock tree becomes minimum;
• a second design section which designs a cell layout in the blocks by taking a placement position of an additional buffer into consideration if there is the additional buffer added by said first design section;
• and
• a third design section which designs a second clock tree in the blocks based on the cell layout designed by said second design section, the second clock tree is designed so that a second clock skew in the second clock tree to be a target is the first clock skew.

A layout design method of designing a layout of a semiconductor IC device, the method comprising:

• a first step of deciding a placement position of a clock buffer to be a basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed and also designing a first clock tree in each block based on the decided placement position of the clock buffer;
• a second step of designing a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided at the first step and based on a delay value of the clock signal propagated in the first clock tree, and further adding an additional buffer;
• and
• a third step of adjusting a placement position of the additional buffer so that the placement position of the additional buffer is in accordance with the placement position of at least one of the cells of the corresponding block if there is the additional buffer added at the second step.

A layout design method of designing a layout of a semiconductor IC device, the method comprising:

• a first step of designing a first clock tree between a plurality of blocks based on a placement position of a clock buffer to be a basis of a clock signal in the blocks and based on a delay value of the clock signal propagated in the first clock tree and a size of each of the blocks, the first clock tree is designed so that a fist clock skew in the first clock tree becomes minimum;
• a second step of designing a cell layout in the blocks by taking a placement position of an additional buffer into consideration if there is the additional buffer added at the first step;
• and
• a third step of designing a second clock tree in the blocks based on the cell layout designed at the second step, the second clock tree is designed so that a second clock skew in the second clock tree to be a target is the first clock skew.

A computer-readable recording medium wherein programs which allow a computer to realize the following sections is recorded thereon;

• a first design section which decides a placement position of a dock buffer to be basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed, and also designs a first clock tree in each block based on the decided placement position of the clock buffer;
• a second design section, which designs a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided by said first design section and based on a delay value of the clock signal propagated in the first clock tree, and for adding an additional buffer;
• and
• an adjustment section which adjusts a placement position of the additional buffer so that the placement position of the additional buffer is in accordance with the placement position of at least one of the cells of the corresponding block if there is the additional buffer added by said second design section.

A computer-readable recording medium wherein programs which allow a computer to realize the following sections is recorded thereon:

• a first design section which decides a first clock tree between a plurality of blocks based on a placement position of a clock buffer to be a basis of a clock signal in the blocks and based on a delay value of the clock signal propagated in the first clock tree and a size of each of the blocks, the first clock tree is designed so that a first clock skew in the first clock tree becomes minimum;
• a second design section which designs a cell layout in the blocks by taking a placement position of an additional buffer into consideration if there is the additional buffer added by said first design section;
• and
• a third design section which designs a second clock tree in the blocks based on the cell layout designed by said second design section, the second clock tree is designed so that a second clock skew in the second clock tree to be a target is the fist clock skew.

A computer-readable recording medium wherein programs which allow a computer to execute the following steps is recorded thereon:

• a first step of deciding a placement position of a clock buffer to be a basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed and also designing a first clock tree in each block based on the decided placement position of a clock buffer;
• a second step of designing a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided at the first step and based on a delay value of the clock signal propagated in the first clock tree, and further adding an additional buffer;
• and
• a third step of adjusting a placement position of the additional buffer so that the placement position of the additional buffer is in accordance with the placement position of a least one of the cells of the corresponding block if there is the additional buffer added at the second step.

A computer-readable recording medium wherein programs which allow a computer to execute the following steps is recorded thereon:

• a first step of designing a first clock tree between a plurality of blocks based on a placement position of a clock buffer to be a basis of a clock signal in the blocks and based on a delay value of the clock signal propagated in the first clock tree and a size of each of the blocks, the first clock tree is designed so that a first clock skew in the first clock tree becomes minimum;
• a second step of designing a cell layout in the blocks by taking a placement position of an additional buffer into consideration if there is the additional buffer added at the first step;
• and
• a third step of designing a second clock tree in the blocks based on the cell layout designed at the second step, the second clock tree is designed so that a second clock skew in the second clock tree to be a target is the first clock skew.

A layout design system of semiconductor IC device, which semiconductor IC device having a plurality of blocks, said system comprising:

• a cell layout fixing section which fixes a cell layout of the blocks;
• a placement deciding section which decides a placement position of a clock buffer, which clock buffer generates a required clock signal in each blocks, in each block whose cell layout has been fixed by said cell layout fixing section;
• a clock tree designing section which designs a clock tree in each block based on the placement of the clock buffer decided by said placement deciding section;
• a delay value calculating section which propagates a clock signal in the blocks and obtains a delay value of the clock signal in each block;
• an intra-block clock tree designing section which designs a clock tree between the blocks based on the placement position of the clock buffer decided by said placement deciding section and also based on the delay value of the clock signal calculated by said delay value calculating section;
• a buffer generating section which generates a buffer in a block in order to adjust a clock skew;
• and
• an adjustment section which adjusts a placement position of a buffer generated by said buffer adding section based on the cell layout.

A layout design system of semiconductor IC device, comprising:

• a first design section which decides a placement position of a clock buffer to be a basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed, and also designs a first clock tree in each block based on the decided placement position of the clock buffer;
• a second design section, which designs a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided by said first design section and based on a delay value of the clock signal propagated in the first clock tree, and for adding an additional buffer;
• and
• an adjustment section which adjusts a placement position of the additional buffer so that the overlap of placement position between the additional buffer and at least one of the cells of the corresponding block is canceled if there is the additional buffer added by said second design section.

A layout design method of designing a layout of a semiconductor IC device, the method comprising:

• a first step of deciding a placement position of a clock buffer to be a basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed, and also designs a first clock tree in each block based on the decided placement position of the clock buffer;
• second step of designing a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided at the first step and based on a delay value of the clock signal propagated in the first clock tree, and further adding an additional buffer, and further adding an additional buffer;
• and
• a third step of adjusting a placement position of the additional buffer so that the overlap of placement position between the additional buffer and at least one of the cells of the corresponding block is canceled if there is the additional buffer added at the second step.

A computer-readable recording medium wherein programs which allow a computer to realize the following sections is recorded thereon:

• a first design section which decides a placement position of a clock buffer to be a basis of a clock signal in each of a plurality of blocks whose cell layout has been fixed, and also designs a first clock tree in each block based on the decided placement position of the clock buffer;
• a second design section, which designs a second clock tree between the blocks based on the placement position of the clock buffer in the blocks decided by said first design section and based on a delay value of the clock signal propagated in the first clock tree, and for adding an additional buffer;
• and
• an adjustment section which adjusts a placement position of the additional buffer so that the overlap of placement position between the additional buffer and at least one of the cells of the corresponding block is canceled if there is the additional buffer added by said second design section.