Timing optimization and timing closure for integrated circuit models

An integrated circuit designed by a method, the method comprising:

• designing an integrated circuit by RTL synthesis with embedded timing analysis and optimization;
• designing an integrated circuit by placement of cells with embedded timing analysis and optimization;
• designing an integrated circuit by routing of interconnect between cells with embedded timing analysis and optimization;
• performing reference timing analysis on the result of the integrated circuit design;
• performing reference timing analysis and embedded timing analysis using a parasitic estimation model, a timing model for arc, timing constraints and exceptions from designer;
• and
• comparing a first slack distribution resulting from a first timing analyses to a second slack distribution resulting from a second timing analyses.

A computer program product, the computer program product encoded in computer readable media, the computer program product comprising:

• a set of instructions, executable on a computer system, configured to:
• design an integrated circuit by RTL synthesis with embedded timing analysis and optimization;
• design an integrated circuit by placement of cells with embedded timing analysis and optimization;
• design an integrated circuit by routing of interconnect between cells with embedded timing analysis and optimization;
• perform reference timing analysis on the result of the integrated circuit design;
• perform reference timing analysis and embedded timing analysis using a parasitic estimation model, a timing model for arc, timing constraints and exceptions from designer;
• and
• compare a first slack distribution resulting from a first timing analyses to a second slack distribution resulting from a second timing analyses.