System and method for identifying finite state machines and verifying circuit designs

A system for identifying a finite state machine (FSM) and verifying a circuit design, in a design description, comprising:

• means for automatically identifying a FSM element in the design description;
• wherein said means for automatically identifying identifies a FSM by finding in the design description a first object which changes or controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object;
• means for importing coverage data which lists an untested element;
• and
• means for generating a test vector for stimulating the untested element.

A computer-readable medium embodying computer program code for causing the computer to identify a finite state machine and verify a circuit design, by performing the steps of:

• automatically, identifying a finite state machine (FSM) element in a design description;
• wherein said automatically identifying step identifies a FSM by fin,ding in the design description a first object which changes or controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object;
• importing coverage data which lists an untested element;
• and
• generating a test vector for stimulating the untested element.

A system for identifying a finite state machine and verifying a circuit design, comprising:

• a design database for storing a design description;
• a test bench, coupled to the design database, for generating a simulated design based on the design description;
• a coverage analysis tool, coupled to receive output data from the test bench, for identifying untested elements in the simulated design;
• and
• a test generator coupled to the design database, the test bench, and the coverage analysis tool, for identifying a finite state machine element in the design description by identifying finite state machine variables in the design description, and generating and sending test vectors to the test bench for exercising the untested elements of the simulated design.