Method of controlling external models in system-on-chip verification
AssigneeInternational Business Machines Corporation
InventorsRobert J. Devins, Robert D. Herzl, David W. Milton, Clarence R. Ogilvie
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Abstract
A method, system and media for communicating with and controlling design logic modules (“cores”) which are external to a system-on-chip (“SOC”) design during verification of the design. An external memory-mapped test device (“EMMTD”) is coupled between a SOC design being tested in simulation, and cores external to the SOC design. Internal logic in the EMMTD provides for control and status monitoring of an external core coupled to an EMMTD bi-directional bus by enabling functions including driving data on the bus, reading the current state of data on the bus, and capturing positive and negative edge transitions on the bus.
Claims41
A method for controlling design elements external to a system-on-chip design, comprising:
- executing software which generates a first signal to an element external to said system-on-chip design;
- and
- providing a hardware description language logic device coupled between said system-on-chip design and said external element, said device receiving said first signal and applying it to said external element.
A system for controlling design elements external to a system-on-chip design, comprising:
- means for executing a test case which generates a first sign to an element external to said system-on-chip design;
- and
- a hardware description language logic device coupled between said system-n-chip design and said external element, said device receiving said first signal and applying it to said external element.
A computer-usable medium storing a simulatable software module comprising a description in a hardware description language, said module when simulated in conjunction with a system-on-chip design being exercised by software which generates a first signal to an element external to said system-on-chip design, simulates a hardware description language logic device coupled between said system-on-chip design and said exit element, said device receiving said first signal and applying it to said external element.
A hardware description language logic device for coupling between a system-on-chip and an element external to said system-on-chip, wherein said system-on-chip generates a first signal to said external element, and said device receives said first signal and applies it to said external element.
Dependencies are inferred from the claim text.