Process, apparatus and program for transforming program language description of an IC to an RTL description
AssigneeLSI Logic Corporation
InventorsAlexander E. Andreev, Ranko Scepanovic
Life of this patent
Estimating the term…
Abstract
An RTL description, such as a Verilog description, of an integrated circuit is derived from a C/C++ description by defining the integrated circuit as a generalized multiplexer having outputs and two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn in which each variable X1, X2, . . . , Xs, is fixed and no output depends on more than one variable of Y1, Y2, . . . , Yn. An output vector is constructed by Exclusive-OR operations to find an index j for UU1=(BIT(0,j), BIT(1,j), . . . , BIT(K−1),j)). The Verilog description of the circuit is a function of the solution of the output vector, or a constant.
Claims20
A process of transforming a program language description of an integrated circuit into an RTL description of the integrated circuit, the program language description functionally describing the integrated circuit in terms of inputs and outputs, the process comprising steps of:
- a) defining the integrated circuit as a generalized multiplexer having two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn, and a plurality of outputs Z such that no output depends on more than one variable of the group consisting of Y1, Y2, . . . , Yn;
- b) fixing each variable X1, X2, . . . , Xs, as X1=a1, X2=a2, . . . , Xs=as, where a1, a2, . . . , as are fixed terms;
- c) constructing an output vector UU as a function of the input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn and the plurality of outputs Z;
- d) if output vector UU has two different bits, constructing a vector UU1 as (BIT(0,j), BIT(1,j), . . . , BIT(K−1,j)), where K is based on the number of Y input terms;
- and
- e) if an index j exists in vector UU1, constructing an RTL description of the integrated circuit as either
- F(a1, at−1, 0, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt)
- OR
- F(a1, at−1,1, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt).
A computer usable medium having a computer readable program embodied therein for addressing data to cause a computer to transform a program language description of an integrated circuit to a hardware description language, the program language description functionally describing the integrated circuit in terms of inputs and outputs, the computer readable program in the computer usable medium comprising:
- first computer readable program code for causing the computer to define the integrated circuit as a multiplexer having two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn, and a plurality of outputs such that no output depends on more than one variable of the group consisting of Y1, Y2, . . . , Yn;
- second computer readable program code for causing the computer to fix each variable X1, X2, . . . , Xs, as X1=a1, X2=a2, . . . , Xs=as;
- third computer readable program code for causing the computer to construct an output vector UU as a function of the input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn and a plurality of outputs Z;
- fourth computer readable program code for causing the computer to identify if vector UU contains two different bits;
- fifth computer readable program code responsive to an identification that vector UU contains two different bits for causing the computer to construct a vector UU1 as (BIT(0,j), BIT(1,j), . . . , BIT(K−1,j), where K is based on the number of Y input terms;
- and
- sixth computer readable program code for causing the computer to construct an RTL description of the multiplexer as
- F(a1, at−1, 0, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt)
- OR
- F(a1, at−1,1, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt).
An apparatus for transforming a program language description of an integrated circuit to a hardware description language, the program language description functionally describing the integrated circuit in terms of inputs and outputs, the apparatus comprising:
- defining means defining the integrated circuit as a multiplexer having two groups of input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn, and a plurality of outputs Z such that no output depends on more than one variable of the group consisting of Y1, Y2, . . . , Yn;
- means for fixing each variable X1, X2, . . . , Xs, as X1=a1, X2=a2, . . . , Xs=as;
- first vector means for constructing an output vector UU as a function of the input variables X1, X2, . . . , Xs and Y1, Y2, . . . , Yn and a plurality of outputs Z;
- identifying means responsive to the first vector means for identifying if vector UU contains two different bits;
- second vector means responsive to the identifying means for constructing a vector UU1 as (BIT(0,j), BIT(1,j), . . . , BIT(K−1,j)), where K is based on the number of Y input terms;
- and
- output means for constructing an RTL description of the multiplexer as
- F(a1, at−1, 0, Xt+1 . . . , Xs,Y1, Y2, . . . , Yn)(Xt)
- OR
- F(a1, at−1,1, Xt+1 . . . , Xs, Y1, Y2, . . . , Yn)(Xt).
Dependencies are inferred from the claim text.