Microcomputer debug architecture and method
AssigneeSTMicroelectronics S.r.l.
InventorDavid Alan Edwards
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AssigneeSTMicroelectronics S.r.l.
InventorDavid Alan Edwards
Estimating the term…
A computer system, including a central processing unit and a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, a set of latches, each latch having an input and an output, and circuitry that couples at least one latch in the set of latches to at least two watchpoints in the set of watchpoints so that there is a predetermined relationship between triggering of the at least two watchpoints. A method of filtering debugging data in a computer system is also provided.
A computer system, comprising:
A method of filtering debugging data in a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of:
Dependencies are inferred from the claim text.