Error recovery mechanism for a high-performance interconnect
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Vicente Enrique Chung, Warren Edward Maule
Life of this patent
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Abstract
An error recovery mechanism for an interconnect is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. In response to a parity error occurring on the bus, the bus slave issues a bus parity error response to the bus master via the bus. After waiting for a predetermined number of bus cycles to allow the bus to idle, the bus master then issues a RESTART bus command packet to the bus slave via the bus to clear the parity error. If the RESTART bus command packet is received correctly, the slave bus will remove the parity error response such that normal bus communication may resume.
Claims20
A method of recovering from an error occurring on a bus within a data processing system, said method comprising the steps of:
- detecting an error on a bus;
- in response to an error occurring on a bus, issuing a bus parity error response by a bus slave via said bus to a bus master;
- waiting for a predetermined number of bus cycles to allow said bus to idle;
- and
- issuing a RESTART bus command packet by said bus master via said bus to said bus slave to clear said parity error response.
A data processing system capable of recovering from a parity error occurring on a bus, comprising:
- means for detecting an error on a bus;
- means for issuing a bus parity error response by a bus slave via said bus to a bus master, in response to a parity error occurring on a bus;
- means for waiting for a predetermined number of bus cycles to allow said bus to idle;
- means for issuing a RESTART bus command packet by said bus master via said bus to said bus slave to clear said parity error response.
A computer program product residing on a computer usable medium for recovering from a parity error occurring on a bus within a data processing system, said computer program product comprising:
- program code means for detecting an error on a bus;
- program code means for issuing a bus parity error response by a bus slave via said bus to a bus master, in response to a parity error occurring on a bus;
- program code means for waiting for a predetermined number of bus cycles to allow said bus to idle;
- program code means for issuing a RESTART bus command packet by said bus master via said bus to said bus slave to clear said parity error response;
- and
- program code means for removing said bus parity error response by said bus slave if said RESTART bus command packet is correctly received by said bus slave, such that normal bus operation may resume.
Dependencies are inferred from the claim text.