Processor having execution core sections operating at different clock rates

A method comprising:

• performing an I/O operation in an I/O ring of a microprocessor at a first clock frequency to access a data item from outside the microprocessor;
• responsive to the I/O operation, performing a first execution operation upon the data item in a first execution sub-core of the microprocessor at a second clock frequency;
• and
• responsive to the first execution operation, performing a second execution operation in a second execution sub-core of the microprocessor at a third clock frequency, the third clock frequency being different than the second clock frequency.

A method comprising:

• inputting an instruction through operation of a first portion of a microprocessor at a first clock frequency;
• performing one or more fetch functions or decode functions associated with the instruction through operation of a second portion of the microprocessor at a second clock frequency;
• and
• performing one or more critical arithmetic logic unit (ALU) functions associated with the instruction through operation of a third portion of the microprocessor at a third clock frequency, the second clock frequency being different than the third clock frequency.