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US 6,487,673 B1Granted
Clock circuit and a computer system having said clock circuit
AssigneeInternational Business Machines Corporation
InventorKohichi Nonomura
Life of this patent
Estimating the term…
Abstract
Described is a clock circuit for supplying synchronized signals to a plurality of circuits. The clock circuit includes a clock generator and a driver for outputting the clock signals inputted from the clock generator with a delay time so that a difference among arrival times of the clock signals is minimized among the plurality of circuits.
Claims11
A clock circuit which supplies clock signals synchronized with each other to a plurality of circuits, comprising:
- a clock generator;
- and
- a driver for outputting each clock signal supplied from clock generator, each signal being outputted with a delay from other signals to corresponding one of said plurality of circuits so that a difference among arrival times of said clock signals is minimized among said plurality of circuits, wherein
- said driver has a plurality of delay times previously determined depending on a load state of each of said circuits, and selects the delay time for each of said circuits supplied with the clock signals, thereby outputting the clock signal after delaying it by the delay time.
1 more element
A computer system comprising:
- a CPU;
- a memory controller;
- a memory;
- and
- a clock circuit for supplying clock signals in synchronization with each other, the clock circuit further comprising:
- a clock generator;
- and
- a driver for receiving clock signals supplied from the clock generator and outputting one or more clock signals with a delay time predetermined in accordance with each circuit of the CPU, the memory controller and the memory to be supplied with the clock signal such that a difference of arrival times of the clock signals among the CPU, the memory controller and the memory is minimized.
5 more elements
A method for supplying clock signals in synchronization with each other to a plurality of circuits, comprising the steps of:
- setting a delay time of the clock signals for each circuit of the plurality of circuits,
- wherein the delay time of the clock signal is set in accordance with a load state of the circuit to be supplied with the clock signal;
- and
- outputting the clock signals with the delay time determined for each circuit so that a difference of arrival times of said clock signal is minimized among the plurality of circuits.
1 more element
Dependencies are inferred from the claim text.