Elimination of turnaround cycles on multiplexed address/data buses

A method for data write operations between an initiator device and a first target device coupled to a bus carrying a clock signal, wherein the clock signal includes a plurality of clock cycles and wherein each clock cycle includes a first and second phase, wherein each of said initiator and first target devices includes a three mode bus driver having three selectable output modes of operation:

• the first mode being a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance, the second mode being a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance, and a third mode having high output impedance, said method comprising the steps of:
• for the driver for the first target device, selecting the third mode of operation during a first and second clock cycle;
• for the driver for the initiator device, selecting the first mode of operation during the first phase of the first clock cycle and driving a first address onto the bus;
• for the driver for the initiator device, selecting the first mode of operation during the first phase of the second clock cycle and driving first data onto the bus;
• and
• for the driver for the initiator device, selecting the second mode of operation during the second phase of the second clock cycle while driving the first data onto the bus.

A method for data write operations between an initiator device and a first target device coupled to a bus having a clock line and a control line, the clock line carrying a clock signal having a plurality of clock cycles wherein each clock cycle includes a first and second phase, the control line carrying a control signal having active and inactive states wherein the active state is asserted when a target device is ready to accept data from the initiator device, the first target device including a three mode bus driver having three selectable output modes of operation:

• the first mode being a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance, the second mode being a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance, and a third mode having high output impedance, the three mode bus driver of the first target device being coupled to the control line of the bus, said method comprising the steps of:
• for the initiator device, placing a first address on the bus during a first clock cycle;
• for the driver of the first target device, selecting the first mode of operation during the first phase of a second clock cycle and driving the control line active;
• for the driver of the first target device, selecting the second mode of operation during the second phase of the second clock cycle while driving the control line active;
• and
• for the initiator device, placing first data on the bus during the second clock cycle.

An information handling system having a data read operation, comprising:

• a bus;
• a clock generator, coupled to said bus, for generating a clock signal that includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase;
• and
• an initiator and a target device coupled to said bus, wherein each of said initiator and target devices includes a three mode bus driver having three selectable output modes of operation:
• the first mode being a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance, the second mode being a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance, and a third mode having high output impedance;
• wherein said initiator device selects the first mode of operation and drives a first address onto said bus during the first phase of a first clock cycle, said initiator device selects the second mode of operation during the second phase of the first clock cycle while driving the first address onto the bus, and said initiator device selects the third mode of operation during a second clock cycle;
• and
• wherein said target device selects the third mode of operation during the first clock cycle, said target device selects the first mode of operation and drives first data onto said bus during the first phase of the second clock cycle, and said target device selects the second mode of operation while driving the first data onto said bus during the second phase of the second clock cycle.

An information handling system having a data write operation, comprising:

• a bus;
• a clock generator, coupled to said bus, for generating a clock signal that includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase;
• and
• an initiator and a first target device coupled to said bus, wherein each of said initiator and target devices includes a three mode bus driver having three selectable output modes of operation:
• the first mode being a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance, the second mode being a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance, and a third mode having high output impedance;
• wherein said initiator device selects the first mode of operation and drives a first address onto said bus during the first phase of a first clock cycle, said initiator device selects the first mode of operation and drives first data onto said bus during the first phase of a second clock cycle, and said initiator device selects the second mode of operation while driving the first data onto said bus during the second phase of the second clock cycle;
• and
• wherein said first target device selects the third mode of operation during the first and second clock cycles.

An information handling system having a data write operation, comprising:

• a bus having a clock line and a control line, the control line carrying a control signal having active and inactive states, wherein the active state is asserted when a device is ready to accept data from another device;
• a clock generator, coupled to said clock line of said bus, for generating a clock signal that includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase;
• and
• an initiator device;
• a first target device including a three mode bus driver having three selectable output modes of operation:
• the first mode being a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance, the second mode being a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance, and a third mode having high output impedance, said three mode bus driver of said first target device being coupled to the control line of said bus;
• wherein said initiator device places a first address on said bus during a first clock cycle, and said initiator device places first data on said bus during a second clock cycle;
• wherein said first target device selects the first mode of operation and drives the control line active during the first phase of the second clock cycle, and said first target device selects the second mode of operation while driving the control line active during the second phase of the second clock cycle.