Virtual shadow registers and virtual register windows

In a processor responsive to interrupts and comprising first and second register sets with said first register set in an active state and said second register set in a shadow state, an active register set switch command, and a DMA/DRA controller operative to transfer data between the shadow register set and memory, a method of reducing context switching in response to interrupts, the method comprising the steps of:

• issuing an interrupt request by a device in said computer system;
• categorizing interrupts into at least a first class and a second class, said first class being a conventional interrupt and said second class being a delayed interrupt;
• when a received interrupt request is categorized as a delayed interrupt, automatically issuing a shadow register to/from memory transfer instruction from said processor to said DMA/DRA controller;
• and
• when the DMA/DRA controller indicates said transfer is complete:
• finishing the current instruction;
• returning information stacked in a conventional manner;
• and
• passing control to the associated interrupt service routine.

In a processor responsive to interrupt requests and comprising first and second register sets with said first register set in an active state and said second register set in a shadow state, an active register set switch mechanism, and a DMA/DRA controller operative to transfer data between the shadow register set and memory, a method of reducing context switching in response to interrupts, the method comprising:

• issuing an interrupt request by a device in said computer system;
• categorizing said interrupt request into at least a first class or a second class, said second class comprising a delayed interrupt;
• when said received interrupt request is categorized in said second class, initiating a register/memory transfer operation to be carried out by said DMA/DRA controller;
• and
• when the DMA/DRA controller indicates said transfer is complete:
• finishing execution of the current instruction;
• retaining return information related to the first instruction stream;
• and
• passing control to a second instruction stream.

In a computer system incorporating a storage device and a processor, said processor comprising an active register set switch mechanism and first and second register sets with the first register set in an active state and the second register set in a shadow state, whereby said processor executes a first instruction stream and is responsive to at least one delayed-interrupt request signal, a method of processing a delayed interrupt comprising:

• receiving said delayed-interrupt request signal and in response thereto, causing context information to be transferred between said storage device and said second register set in parallel with at least a portion of the execution of said first instruction stream;
• and
• when said act of transferring is complete:
• finishing execution of the current instruction;
• retaining return information related to the first instruction stream;
• and
• passing control to a second instruction stream.

A method of operating a computer system, comprising:

• executing a first stream of instructions while interacting with an first register set, said first register set being in an active state;
• receiving an interrupt request signal;
• categorizing said interrupt request signal to be of one of a plurality of categories;
• in response to the categorization, determining the interrupt request signal to be a member of the delayed-interrupt category;
• in response to the determination, causing context information to be transferred between a storage device and a second register set in parallel with at least a portion of the execution of a first instruction stream, whereby said second register set is in a shadow state;
• and
• when said transfer is complete:
• finishing the current instruction of the first instruction stream;
• saving return information related to the first instruction stream into a data structure in memory;
• and
• passing control to a second instruction stream, the second instruction stream initiated in response to the delayed interrupt request.

A computer-implemented method comprising:

• executing a first instruction stream that causes register transfer operations in said first instruction stream to cause a first register set to be accessed;
• receiving a delayed-interrupt request signal and in response thereto, causing information to be transferred between a storage device and a second register set in parallel with at least a portion of the execution of a first instruction stream;
• and
• when said transfer is at least partially complete, passing control to a second instruction stream.

A computer-implemented method of delayed interrupt processing, comprising:

• executing a first instruction stream that causes said processor to access a first register set;
• receiving a delayed-interrupt request, and in response thereto, causing information to be transferred between a data structure in memory and a second register set, said transfer overlapping in time with at least a portion of said act of executing;
• and
• passing control to a second instruction stream that executes at least one instruction that causes said processor to access said second register set.

A computer-implemented method, comprising:

• executing an instruction stream that causes said processor to access a first register set;
• receiving an interrupt request, and in response thereto, transferring at least one datum between a data structure in memory and a second register set, said transfer overlapping in time with at least a portion of said act of executing;
• and
• accessing said second register set.

A computer-implemented comprising:

• receiving an interrupt request;
• categorizing said interrupt request into one of at least two classes, a first class of interrupts, and a second class of interrupts, whereby said second class of interrupts comprises at least one delayed interrupt;
• automatically initiating, when said interrupt request is categorized as a delayed interrupt, at least one shadow register set transfer operation that transfers data between a storage device and a shadow register set;
• and
• when said machine context has been loaded:
• finishing execution of the current instruction;
• and
• branching to a program entry point.