Method and apparatus for denormal load handling

A method for loading denormal floating point values into a microprocessor, the method comprising:

• reading floating point data from a data bus;
• classifying the floating point data as denormal or normal;
• converting the floating point data to a predetermined format in a first number of clock cycles in response to the floating point data being normal;
• converting the floating point data to the predetermined format in a second number of clock cycles in response to the floating point data being denormal;
• and
• converting subsequent floating point data received after the denormal floating point data in the second number of clock cycles regardless of whether the subsequent floating point data is denormal or normal.

A computer system comprising:

• a memory;
• a communications device for transmitting and receiving data across a network;
• and
• a microprocessor coupled to the memory and the communications device, wherein the microprocessor comprises:
• a classification unit configured to receive floating point data from floating point load operations and determine the floating point data's type, wherein the classification unit is configured to assert a denormal control signal in response to the floating point data's type being denormal;
• a conversion unit configured to receive the floating point data and convert the floating point data to a predetermined format, wherein the conversion unit is configured to convert the floating point data to the predetermined format in a first number of clock cycles if the floating point data is normal, wherein the conversion unit is configured to convert the floating point data to the predetermined format in a second number of clock cycles if the floating point data is denormal, wherein the first number of clock cycles is less than the second number of clock cycles;
• and
• a reissue buffer configured to temporarily store floating point instructions for at least one clock cycle, wherein the reissue buffer is configured to replay the stored floating point instructions in response to receiving the asserted denormal control signal;
• wherein in response to receiving the denormal floating point data, the conversion unit is further configured to convert normal floating point data and denormal floating point data using the second number of clock cycles until the conversion unit experiences an idle clock cycle.