US 6,487,651 B1Granted

MIMD arrangement of SIMD machines

AssigneeAssabet Ventures

InventorsJames H. Jackson, Michael W. Kleeman, Georges Melhem, Sanjeev Mohindra

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Abstract

An SIMD array processor having a scalable and flexible architecture. The SIMD array architecture includes an array of processing elements, a plurality of processor controllers, and at least one other computer system. A system area network interconnects at least one user computer with the processor controllers and the computer system; and, a storage area network interconnects at least one storage device with the processor controllers and the computer system. The SIMD array architecture is adapted to allow different user computers to use different portions of the array of processing elements and/or different processor controllers and computer systems simultaneously. The array of processing elements has a hierarchical structure comprising backplanes, PCB's, ASIC's, and arrays of processing elements. The SIMD array architecture can be scaled by increasing the quantity of backplanes, PCB's, ASIC's, and/or by increasing the size of the arrays of processing elements. The SIMD array architecture can also be flexibly modified to achieve arrays of processing elements with different aspect ratios by selectively accessing data paths interconnecting the processing elements.

Claims2

Dependent claims

A method of operating a computing system, the computing system comprising an array of processing elements and a plurality of processor controllers, at least one of the plurality of processor controllers having an interface to a communications link, and at least one of the plurality of processor controllers being adapted to control the plurality of processor controllers and at least a portion of the array of processing elements, the method comprising the steps of:

receiving at least one command at the interface of a first processor controller;
translating the command to an instruction sequence by the first processor controller;
in the event it is determined by the first processor controller that a first portion of the instruction sequence is executable in a SIMD mode by the array of processing elements, providing the first portion of the instruction sequence to at least a portion of the array of processing elements by the first processor controller, and executing the first portion of the instruction sequence by the array of processing elements;
and
in the event it is determined by the first processor controller that a second portion of the instruction sequence is executable in a MIMD mode by at least one of the plurality of processor controllers, providing the second portion of the instruction sequence to at least one of the plurality of processor controllers by the first processor controller, and executing the second portion of the instruction sequence by the at least one of the processor controllers.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/696,078Filed 25 Oct 2000 · us provisional application
Priority: 26 Oct 1999
Granted: 26 Nov 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H04L 67/1097
In which an application is distributed across nodes in the network: for distributed storage of data in networks, e.g. transport arrangements for…
G06F 15/17337
Using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake: direct connection machines, e.g. completely connected computers,…
G06F 15/17381
Non hierarchical topologies: two dimensional, e.g. mesh, torus
G06F 15/8023
Single instruction multiple data [SIMD] multiprocessors: two dimensional arrays, e.g. mesh, torus