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US 6,487,647 B1Granted
Adaptive memory interface timing generation
AssigneeIntel Corporation
InventorEric C. Samson
Life of this patent
Estimating the term…
Abstract
The invention, in one embodiment, is a method of operating a synchronous memory device generally comprising providing a clock signal to the synchronous memory device to time the operation thereof and adapting the timing of at least one of reads from and writes to the synchronous memory device to improve timing parameters for the operation thereof.
Claims24
A method comprising:
- generating a clock signal from a clock synthesizer having a plurality of phase taps;
- inputting the clock signal to a memory device to control the memory device;
- determining one or more of the plurality of phase taps with which data is to be validly written to or read from the memory device;
- selecting one of the plurality of phase taps determined to have valid data to generate a timing signal;
- and
- controlling with the timing signal a register in which data to be written to the memory device is to be stored, in which data to be read from the memory device is to be stored, or in which data to be written and read are both to be stored.
3 more elements
An apparatus comprising:
- a memory device;
- and
- an electronic device coupled to the memory device by a bus, in which the electronic device includes a clock synthesizer having a plurality of phase taps, the clock synthesizer to,generate a clock signal to control the memory device;
- and
- the electronic device to determine one or more of the plurality of phase taps with which data is to be valid when written from or read to one or more registers and to select one that provides valid data.
2 more elements
A program storage device encoded with instructions that, when executed by a computer, perform a method comprising:
- programming a clock synthesizer having a plurality of phase taps to generate a clock signal to be input to a memory device to control the memory device;
- and
- determining one or more of the plurality of phase taps with which data may be validly written to and read from the memory device
- selecting one of the plurality of phase taps determined to have valid written and read data.
1 more element
Dependencies are inferred from the claim text.