Semiconductor memory for operation in a plurality of operational modes
AssigneeFujitsu Limited
InventorHidetaka Shibata
Life of this patent
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Abstract
A semiconductor memory includes an instruction decoder, a register for storing operational mode information, a memory core for storing data, and a mode set-up control circuit. The memory operates in a number of modes, such as a read mode, a write mode and a set-up mode. When performing a read or a write command, access information for the command is stored in the register. In order to operate the memory more efficiently, the mode set-up control circuit prestores memory access information. Then, at the end of a read or write command, the prestored access information is loaded into the register. Locally storing the access information prevents the memory from having to wait to receive such information from an external element.
Claims14
A semiconductor memory for operation in a plurality of operational modes including at least a read, a write and a set up mode, the semiconductor memory comprising:
- an instruction decoder, receiving an instruction code signal for setting up one of the plurality of operational modes, receiving a mode set-up instruction signal for modifying operational mode information defining a previously set up operational mode, and decoding the instruction code signal and the mode set-up instruction signal;
- at least one register connected to the instruction decoder for storing the operational mode information corresponding to the decoded instruction code signal;
- a memory core for storing data, wherein the memory core is accessed in the operational mode which is set up;
- and
- a mode set-up control circuit connected to the instruction decoder, wherein the mode set-up control circuit receives the decoded mode set-up instruction signal and loads the operational mode information corresponding to the decoded mode set-up instruction signal into the register in response to the termination of the previously set up operational mode.
A method of loading operational mode information for a semiconductor memory which is adapted to operate in a plurality of operational modes including at least a read, a write and a set-up mode operation, the method comprising the steps of:
- loading the operational mode information in a register;
- collectively providing an instruction code signal which sets up one of the plurality of operational modes in accordance with the operational mode information and a mode set-up instruction signal for modifying the operational mode information defining the previously set up operational mode;
- executing an operation specified by the operational mode which is set up;
- and
- reloading the operational mode information in accordance with the mode set-up instruction signal immediately after the termination of the operation.
Dependencies are inferred from the claim text.