Method and apparatus of bus interface for a processor

A method of interfacing buses to a processor, the method comprising:

• storing bytes of data from a first bus into a plurality of first buffers;
• storing bytes of data from a second bus into a plurality of second buffers;
• writing an enable byte into a byte enable buffer;
• and
• in response to the enable byte,
• enabling a plurality of first tri-state drivers to selectively output bytes of data from the plurality of first buffers to the processor, and,
• enabling a plurality of second tri-state drivers to selectively output bytes of data from the plurality of second buffers to the processor.

A parallel bus interface for a processor comprising:

• a first means for storing bytes of parallel data from a first parallel bus;
• a second means for storing bytes of parallel data from a second parallel bus;
• and
• a means for selectively outputting bytes of parallel data stored in the first means and the second means to the processor.

A bus interface for a processor comprising:

• a first means for storing bytes of data from a first bus;
• a second means for storing bytes of data from a second bus;
• and
• a means for selectively outputting bytes of data stored in the first means and the second means to the processor, wherein the means for selectively outputting bytes of data is a byte enable buffer.

A bus interface for a processor comprising:

• a first means for storing bytes of data from a first bus;
• a second means for storing bytes of data from a second bus;
• a means for selectively outputting bytes of data stored in the first means and the second means to the processor;
• a third means for driving bytes of data from the first means for storing bytes of data to the processor;
• and
• a fourth means for driving bytes of data from the second means for storing bytes of data to the processor.

A bus interface for a processor comprising:

• a first byte storage means for storing bytes of data from a first bus;
• a first driver means to couple to the first byte storage means and the processor, the first driver means for driving at least one byte of data;
• a second byte storage means for storing bytes of data from a second bus;
• a second driver means to couple to the second byte storage means and the processor, the second driver means for driving at least one byte of data;
• and
• a byte enable means coupled to the first and second driver means, the byte enable means for selectively outputting bytes of data stored in the first storage means to the processor and for selectively outputting bytes of data stored in the second storage means to the processor.