Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle

A bus interface unit, comprising:

• a first bus controller coupled to receive a first request (A) across a first bus from a first bus agent;
• a second bus controller coupled to receive a second request (B) across a second bus from a second bus agent, wherein the first request is to a modified cache line within the second bus agent, and wherein the second request is to a modified cache line within the first bus agent;
• and
• an arbiter coupled to the first bus controller and the second bus controller to allow completion of a transaction originating from the first request and to allow completion of a snoop request cycle originating from the second bus agent before granting mastership to the second bus.

A computer, comprising:

• a first bus coupled to receive a first request from a first bus agent coupled to the first bus;
• a second bus coupled to receive a second request from a second bus agent coupled to the second bus;
• wherein the first request is to a modified address within a cache memory of the second bus agent, and wherein the second request is to a modified address within a cache memory of the first bus agent;
• an arbiter coupled to maintain mastership of the first bus such that the first bus can complete a response to the first request and can complete a snoop request issued from the second bus agent to the cache memory of the first bus agent before allowing the second request to be issued across the second bus;
• and
• a peripheral device adapted for communication with the first and second buses, and coupled upon a printed circuit board separate from another printed circuit board upon which the arbiter is coupled.

A computer comprising:

• a peripheral controller means arranged upon a first printed circuit board;
• a first and second bus agent means coupled to a second printed circuit board separate from the first printed circuit board and further coupled to respective first and second buses;
• and
• means for granting mastership of the first bus to allow a transaction from the first bus agent and a snooping cycle to occur across the first bus before granting mastership to the second bus.

A method for orchestrating transactions upon a bus within a multi-processor system, the method comprising:

• dispatching a request cycle from a first bus agent across a first bus to a modified address within a second bus agent;
• deferring a request cycle from the second bus agent across a second bus to a modified address within the first bus agent;
• and
• servicing a first snoop cycle dispatched across the first bus to the first bus agent before retrying the deferred request cycle.