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US 6,487,615 B1Granted
Apparatus and method for accepting physical write package when the posted write error queue is full
AssigneeIntel Corporation
InventorMikal C. Hunsaker
Life of this patent
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Abstract
A system for handling write requests is described. The system uses two queues for storing posted write requests. When a posted write error results, software handles the posted write error using information stored in a first queue of the two queues. The write request producing the posted write error is cleared from the second queue which continues to handle physical packets containing write requests.
Claims20
A circuit for handling memory access requests, comprising:
- a general First-In, First-Out (FIFO) memory to store write requests from a bus;
- a first memory queue in communication with the general FIFO to receive write requests from the general FO for use by software in the event that an error results when executing the write request and the write request is handled as a posted write request, and
- a second memory queue coupled to the general FIFO to receive the write request from the general FIFO, the write requests in the second memory queue for use by a physical response DMA executing the write request.
A circuit for handling memory access requests, comprising:
- a memory device to store physical packets including data associated with write requests;
- a first queue to store data associated with a write request for processing when the write request being handled as a posted write request fails;
- and
- a second queue to receive data associated with a write request even when the first queue is fill.
1 more element
Dependencies are inferred from the claim text.