Zero anticipation method and apparatus
AssigneeTexas Instruments Incorporated
InventorsJean-Pierre Giacalone, Herve Catan, Anne Lombardot
Life of this patent
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Abstract
A zero anticipation mechanism for an arithmetic unit 42 of a processing engine includes an array of cells 420, 430 interconnected to produce an ordered sequence of intermediate anticipation signals. The array of cells includes cells connected to receive intermediate result signals from the arithmetic unit, cells for forwarding an intermediate anticipation signal supplied thereto, and cells for generating a combination of first intermediate anticipation signals and second intermediate anticipation signals supplied thereto. The zero anticipation mechanism implements a zero look-ahead mechanism which can predict a zero result 479 prior to the arithmetic unit completing an arithmetic operation.
Claims22
A digital system with a processing engine, the processing engine comprising an arithmetic unit connected to a zero anticipation mechanism, the zero anticipation mechanism having an array of cells interconnected to produce an ordered sequence of intermediate anticipation signals comprising:
- first cells connected to receive intermediate result signals from the arithmetic unit, each first cell having at least one output for providing an intermediate anticipation signal;
- and
- second cells for generating a combination of a first intermediate anticipation signal and a second intermediate anticipation signal supplied thereto, each second cell having inputs connected respectively to receive the first intermediate anticipation signal and the second intermediate anticipation signal from adjacent first cells or second cells, each second cell having at least one output for providing an intermediate anticipation signal;
- and
- wherein a selected one of the array of cells has an output for providing a zero anticipation signal.
A method of anticipating a zero result of an arithmetic unit of a processing engine, the method comprising the steps of:
- providing input data to the arithmetic unit;
- generating intermediate result signals for the arithmetic unit;
- producing an ordered sequence of intermediate anticipation signals by receiving the intermediate result signals from the arithmetic unit to form intermediate anticipation signals;
- and
- selectively forwarding and combining intermediate anticipation signals in accordance with a predetermined algorithm for generating a zero anticipation signal.
A method of anticipating a zero result of an arithmetic unit of a processing engine, the method comprising the steps of:
- grouping adjacent bit positions of the arithmetic unit into sections, with each section containing at least two bit positions;
- providing input data to the arithmetic unit;
- generating intermediate anticipation signals for each section;
- grouping intermediate anticipation signals for each section;
- and
- combining the grouped intermediate signals for each section to form a zero anticipation signal.
Dependencies are inferred from the claim text.