Early completion of iterative division
AssigneeAdvanced Micro Devices, Inc.
InventorStuart F. Oberman
Life of this patent
Estimating the term…
Abstract
A multiplier configured to execute division and square root operations by executing iterative multiplication operations is disclosed. The multiplier is configured to complete divide-by-two and zero dividend instructions in fewer clock cycles by detecting them before or during the first iteration and then performing an exponent adjustment and rounding the result to the desired precision. A system and method for rapidly executing divide-by-two and zero dividend instructions within the context of a multiplier that executes division and square root instructions using iterative multiplication are also disclosed.
Claims19
A floating point unit configured to divide a dividend by a divisor using iterative multiplication operations, said floating point unit comprising:
- a divide-by-two detection unit configured to detect when said divisor is an integer power of two,
- a reciprocal calculation unit coupled to said divide-by-two detection unit, wherein said reciprocal calculation unit is configured to calculate an exact reciprocal of said divisor in response to said divisor being an integer power of two, and
- a multiplier coupled to said divide-by-two detection unit and said reciprocal calculation unit, wherein said multiplier is configured to perform a first multiplication operation by multiplying said exact reciprocal and said dividend to form a first product.
A method for executing floating point division instructions in a floating point unit, said method comprising:
- generating a reciprocal of a divisor using iterative multiplication operations;
- detecting divide instructions that specify a divisor that is an integer power of two;
- calculating an exact reciprocal of the divisor in response to said divisor being an integer power of two;
- and
- multiplying the exact reciprocal and a dividend of the divide instruction to form a first product.
A computer system comprising:
- a main memory;
- a communications device;
- a system bus;
- and
- a microprocessor, wherein said microprocessor, said main memory, and said communications device are coupled via the system bus, and wherein the microprocessor comprises a floating point unit, wherein the floating point unit comprises:
- a divide-by-two detection unit configured to detect when said divisor is an integer power of two,
- a reciprocal calculation unit coupled to said divide-by-two detection unit, wherein said reciprocal calculation unit is configured to calculate an exact reciprocal of said divisor in response to said divisor being an integer power of two, and
- a multiplier coupled to said divide-by-two detection unit and said reciprocal calculation unit, wherein said multiplier is configured to perform a first multiplication operation by multiplying said exact reciprocal and said dividend to form a first product.
Dependencies are inferred from the claim text.